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RTSD
HDL
Commits
5935840c
Commit
5935840c
authored
5 years ago
by
Reinier van der Walle
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Pushed changes of dp_fifo_fill_eop made on branch
STAT-263
to master as
it is already needed for tr_10_GbE
parent
a80e43c8
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Changes
1
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libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+24
-20
24 additions, 20 deletions
libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
with
24 additions
and
20 deletions
libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+
24
−
20
View file @
5935840c
...
...
@@ -122,7 +122,7 @@ ARCHITECTURE rtl OF dp_fifo_fill_eop IS
SIGNAL
received_eop
:
BOOLEAN
:
=
FALSE
;
SIGNAL
nxt_received_eop
:
BOOLEAN
:
=
FALSE
;
SIGNAL
crossed_domain_snk_in_eop
:
STD_LOGIC
:
=
'0'
;
BEGIN
-- Output monitor FIFO filling
...
...
@@ -136,6 +136,7 @@ BEGIN
rd_fill_ctrl
<=
rd_fill_32b
(
c_fifo_size_w
-1
DOWNTO
0
);
gen_dp_fifo_sc
:
IF
g_use_dual_clock
=
FALSE
GENERATE
crossed_domain_snk_in_eop
<=
snk_in
.
eop
;
u_dp_fifo_sc
:
ENTITY
work
.
dp_fifo_sc
GENERIC
MAP
(
g_technology
=>
g_technology
,
...
...
@@ -174,6 +175,16 @@ BEGIN
END
GENERATE
;
gen_dp_fifo_dc
:
IF
g_use_dual_clock
=
TRUE
GENERATE
u_common_spulse
:
ENTITY
common_lib
.
common_spulse
PORT
MAP
(
in_rst
=>
wr_rst
,
in_clk
=>
wr_clk
,
in_pulse
=>
snk_in
.
eop
,
out_rst
=>
rd_rst
,
out_clk
=>
rd_clk
,
out_pulse
=>
crossed_domain_snk_in_eop
);
u_dp_fifo_dc
:
ENTITY
work
.
dp_fifo_dc
GENERIC
MAP
(
g_technology
=>
g_technology
,
...
...
@@ -232,8 +243,12 @@ BEGIN
xon_reg
<=
nxt_xon_reg
;
state
<=
nxt_state
;
i_src_out
<=
nxt_src_out
;
IF
crossed_domain_snk_in_eop
=
'1'
THEN
received_eop
<=
TRUE
;
ELSE
received_eop
<=
nxt_received_eop
;
END
IF
;
END
IF
;
END
PROCESS
;
nxt_xon_reg
<=
src_in
.
xon
;
-- register xon to easy timing closure
...
...
@@ -242,7 +257,7 @@ BEGIN
p_state
:
PROCESS
(
state
,
rd_sosi
,
src_in
,
xon_reg
,
rd_fifo_usedw
,
rd_fill_ctrl
,
received_eop
)
BEGIN
nxt_state
<=
state
;
nxt_received_eop
<=
received_eop
;
rd_siso
<=
src_in
;
-- default acknowledge (RL=1) this input when output is ready
-- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
...
...
@@ -252,12 +267,6 @@ BEGIN
nxt_src_out
.
eop
<=
'0'
;
nxt_src_out
.
sync
<=
'0'
;
IF
snk_in
.
eop
=
'1'
THEN
nxt_received_eop
<=
TRUE
;
ELSE
nxt_received_eop
<=
received_eop
;
END
IF
;
CASE
state
IS
WHEN
s_idle
=>
IF
xon_reg
=
'0'
THEN
...
...
@@ -329,6 +338,7 @@ BEGIN
p_state
:
PROCESS
(
state
,
src_in
,
xon_reg
,
pend_src_out
,
rd_fifo_usedw
,
rd_fill_ctrl
,
received_eop
)
BEGIN
nxt_state
<=
state
;
nxt_received_eop
<=
received_eop
;
hold_src_in
<=
src_in
;
-- default request (RL=1) new input when output is ready
...
...
@@ -339,12 +349,6 @@ BEGIN
nxt_src_out
.
eop
<=
'0'
;
nxt_src_out
.
sync
<=
'0'
;
IF
snk_in
.
eop
=
'1'
THEN
nxt_received_eop
<=
TRUE
;
ELSE
nxt_received_eop
<=
received_eop
;
END
IF
;
CASE
state
IS
WHEN
s_idle
=>
IF
xon_reg
=
'0'
THEN
...
...
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