-Moved all UNB1 dependencies to ctrl_unb1_board. This should allow simple

 migration to another board by simply creating a new ctrl_unb1_board equivalent.

applications/arts/designs/arts_unb1_sc1/src/generated/arts_unb1_sc1_bg_single_pol_pins.tcl

+
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl

applications/arts/designs/arts_unb1_sc1/src/generated/hdllib.cfg

 hdl_lib_name = arts_unb1_sc1_bg_single_pol
 hdl_library_clause_name = arts_unb1_sc1_bg_single_pol_lib
 hdl_lib_uses_synth = common dp mm diag bf unb1_board 
-hdl_lib_technology = ip_stratixiv
 synth_files =
     ../arts_unb1_sc1_offload.vhd
     ../generated/mm_master.vhd
@@ -11,11 +10,15 @@ test_bench_files =
     tb_arts_unb1_sc1_bg_single_pol.vhd
 quartus_copy_files =
     qsys_mm_master.qsys .
+
+hdl_lib_technology = ip_stratixiv
 quartus_qsf_files =
     $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 quartus_sdc_files =
+
 $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1_bg_single_pol/qsys_mm_master/synthesis/qsys_mm_master.qip
+    $HDL_BUILD_DIR/unb2/quartus/arts_unb1_sc1_bg_single_pol/qsys_mm_master/synthesis/qsys_mm_master.qip
 quartus_tcl_files =
     arts_unb1_sc1_bg_single_pol_pins.tcl

tools/oneclick/components/component.py

@@ -48,37 +48,6 @@ LIBRARY dp_lib;
     USE dp_lib.dp_stream_pkg.ALL;
 """
 
-#ENTITY_TEMPPLATE = """
-#ENTITY DESIGN_NAME IS
-#  GENERIC (
-#    g_sim : BOOLEAN := FALSE; -- Overridden by simulation test bench
-# );
-#  PORT (
-#    -- GENERAL
-#    CLK           : IN    STD_LOGIC; -- System Clock
-#    PPS           : IN    STD_LOGIC; -- System Sync
-#    WDI           : OUT   STD_LOGIC; -- Watchdog Clear
-#    INTA          : INOUT STD_LOGIC; -- FPGA interconnect line
-#    INTB          : INOUT STD_LOGIC; -- FPGA interconnect line
-#                  
-#    -- Others     
-#    VERSION       : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
-#    ID            : IN    STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
-#    TESTIO        : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-#    
-#    -- I2C Interface to Sensors
-#    sens_sc       : INOUT STD_LOGIC;
-#    sens_sd       : INOUT STD_LOGIC;
-#  
-#    -- 1GbE Control Interface
-#    ETH_clk       : IN    STD_LOGIC;
-#    ETH_SGIN      : IN    STD_LOGIC;
-#    ETH_SGOUT     : OUT   STD_LOGIC
-# );
-#END DESIGN_NAME;
-#
-#"""
-
 ENTITY_DECLARATION_TOP= """
 ENTITY DESIGN_NAME IS
   GENERIC (
@@ -233,6 +202,10 @@ class Component(mp.Process):
 
         self.vhdl_name_comment_block = NAME_COMMENT_BLOCK.replace('$name', self.name)
 
+        self.tcl_pin_files = ''
+        self.hdllib_entries = ''
+        self.hdllib_entries_sdc = ''
+
         self.hdllib_used_libs = 'common dp mm '
 
         self.mm_regs = []
@@ -459,7 +432,6 @@ class Component(mp.Process):
             hdllib_file.write('hdl_lib_name = %s\n' %self.name)
             hdllib_file.write('hdl_library_clause_name = %s_lib\n' %self.name)
             hdllib_file.write('hdl_lib_uses_synth = %s\n' %self.hdllib_used_libs)
-            hdllib_file.write('hdl_lib_technology = ip_stratixiv\n')
             hdllib_file.write('synth_files =\n')
             for component in self.components:
                 if component.vhdl_file_name != None:
@@ -474,14 +446,19 @@ class Component(mp.Process):
             hdllib_file.write('quartus_copy_files =\n')
             hdllib_file.write('    qsys_mm_master.qsys .\n')
  
-            hdllib_file.write('quartus_qsf_files =\n')
-            hdllib_file.write('    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf\n')
+            for component in self.components:
+                hdllib_file.write(component.hdllib_entries)
         
             hdllib_file.write('quartus_sdc_files =\n')
-            hdllib_file.write('    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc\n')
+            for component in self.components:
+                hdllib_file.write(component.hdllib_entries_sdc)  
  
+            # FIXME QSYS MM master QIP path depends on board...we should get rid of that.
+            # . Put both options here as workaround. We don't want to forward self.name to either mm_master.py or ctrl_unb_common.
+            # . Also, we don't want QSYS stuff in ctrl_unb_common or ctrl_unb_common stuff in mm_master.
             hdllib_file.write('quartus_qip_files =\n')
             hdllib_file.write('    $HDL_BUILD_DIR/unb1/quartus/%s/qsys_mm_master/synthesis/qsys_mm_master.qip\n' %self.name)
+            hdllib_file.write('    $HDL_BUILD_DIR/unb2/quartus/%s/qsys_mm_master/synthesis/qsys_mm_master.qip\n' %self.name)
     
             hdllib_file.write('quartus_tcl_files =\n')
             hdllib_file.write('    %s_pins.tcl\n' %self.name)
@@ -492,10 +469,8 @@ class Component(mp.Process):
             # Pin TCL file
             ############################################################################### 
             pin_file = open('generated/%s_pins.tcl' %self.name, "w")
-            pin_file.write('source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl\n')
-            pin_file.write('source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl\n')
-            pin_file.write('source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl\n')
-            pin_file.write('source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl\n')
+            for component in self.components:
+                pin_file.write(component.tcl_pin_files)
             pin_file.close()
 
             for component in self.components: # Chance for subcomponents to run their own overloaded generate()

tools/oneclick/components/ctrl_unb1_board.py

@@ -161,11 +161,33 @@ VHDL_LIB = """LIBRARY unb1_board_lib; --ctrl_unb1_board
     USE unb1_board_lib.unb1_board_pkg.ALL;
 """
 
+TCL_PIN_FILES = """
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+"""
+
+
+HDLLIB_ENTRIES = """
+hdl_lib_technology = ip_stratixiv
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+"""
+
+HDLLIB_ENTRIES_SDC = """
+$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+"""
 
 class ctrl_unb1_board(Component):
     def __init__(self, nof_streams=1, data_width=32, inst_nr=None):
         Component.__init__(self, inst_nr=inst_nr, name='ctrl_unb1_board')
 
+        self.tcl_pin_files = TCL_PIN_FILES
+        self.hdllib_entries = HDLLIB_ENTRIES
+        self.hdllib_entries_sdc = HDLLIB_ENTRIES_SDC
+
+
         self.vhdl_file_name = None
 
         self.set_vhdl_strings(self, VHDL_INST, VHDL_CONSTANTS, VHDL_SIGNALS, VHDL_LIB)