-Stripped down the TB to the bare minimum (fixed wrong stimuli count

increments);
-Separated RD from WR RAM pointer and within RD also separated MISO and
MOSI RAM pointer. This implements correct latencies.

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -18,10 +18,37 @@
 --
 -------------------------------------------------------------------------------
 
-
--- Author: Daniel van der Schuur
+-- Author: 
+-- . Daniel van der Schuur
+-- . Jan Oudman (first version)
 -- Purpose: 
-
+-- . Count incoming data values and keep the counts in RAM as a histogram
+-- Description: 
+--  . The block schematic below shows the data flow from snk_in to ram_mosi:
+--    . snk_in.data is interpreted as address (bin) to read from RAM by bin_reader.
+--      . a RAM pointer 0 or 1 is kept as MS part of the address.
+--        . snk_in.sync determines the RAM pointer 0 or 1.
+--    . The data read from that adress, the bin count, is incremented and written
+--      back by bin_writer.
+--    . bin_arbiter decides whether a read or write accessw takes precedence, in case
+--      of simultanious RAM access requests by both bin_reader and bin_writer.
+--    . Upon request (ram_miso), the bin counts (the histogram) are output on 
+--      ram_mosi.
+--                             bin_reader_miso    bin_arbiter_rd_miso             
+--               __________    |   ___________    |   ___________                 
+--              |          |   |  |           |   |  |           |                
+-- ---snk_in--->|bin_reader|<--+--|           |<--+--|           |                
+--              |__________|      |           |      |           |                
+--                   |            |           |      |           |                
+--                   |            |           |      |           |                
+--     bin_reader_to_writer_mosi  |bin_arbiter|      | RAM(1..0) |----ram_mosi--->
+--                   |            |           |      |           |                
+--               ____v_____       |           |      |           |                
+--              |          |      |           |      |           |                
+--              |bin_writer|---+->|           |---+->|           |                
+--              |__________|   |  |___________|   |  |___________|                
+--                             |                  |                               
+--                             bin_writer_mosi    bin_arbiter_wr_mosi             
 
 LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -76,6 +103,10 @@ ARCHITECTURE rtl OF st_histogram IS
   -------------------------------------------------------------------------------
   -- bin_arbiter
   -------------------------------------------------------------------------------
+  SIGNAL bin_arbiter_wr_ram_pointer     : STD_LOGIC;
+  SIGNAL bin_arbiter_rd_ram_pointer     : STD_LOGIC;
+  SIGNAL prv_bin_arbiter_rd_ram_pointer : STD_LOGIC;
+
   SIGNAL write_allowed           : BOOLEAN;
 
   SIGNAL nxt_bin_arbiter_wr_mosi : t_mem_mosi;
@@ -110,7 +141,7 @@ BEGIN
   -- . Target either RAM 0 or 1 per sync period
   -- . RD/WR sides of RAM have shifted sync periods due to rd>wr latency
   --   . e.g. a new sync period is read while an old sync period is written
-  --   . Solution: treat the RAM pointer as MS address bit
+  --   . Solution: treat the RAM pointer as MS address bit in separate RD/WR buses
   --   . ram_pointer is synchronous to snk_in.sync
   -------------------------------------------------------------------------------
   p_ram_pointer : PROCESS(dp_rst, dp_clk) IS
@@ -229,16 +260,31 @@ BEGIN
   --         . bin_arbiter_wr_mosi.address
   --         . bin_arbiter_rd_mosi.address 
   -------------------------------------------------------------------------------
- 
+  bin_arbiter_wr_ram_pointer <= bin_arbiter_wr_mosi.address(8); --FIXME (8) is not generic
+  bin_arbiter_rd_ram_pointer <= bin_arbiter_rd_mosi.address(8);  
+
+  -- Store the previous RAM pointer of the read bus
+  p_prv_ram_pointer : PROCESS(dp_clk, dp_rst) IS
+  BEGIN
+    IF dp_rst = '1' THEN
+      prv_bin_arbiter_rd_ram_pointer <= '0';
+    ELSIF RISING_EDGE(dp_clk) THEN
+      prv_bin_arbiter_rd_ram_pointer <= bin_arbiter_rd_ram_pointer;
+    END IF;
+  END PROCESS;
+
   -- Let bin_arbiter write RAM 0 while user reads RAM 1 and vice versa
-  common_ram_r_w_wr_mosi_arr(0) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_mosi.address(8)='0' ELSE histogram_wr_mosi; --FIXME (8) is not generic
-  common_ram_r_w_rd_mosi_arr(0) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_mosi.address(8)='0' ELSE histogram_rd_mosi;
-  common_ram_r_w_wr_mosi_arr(1) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_mosi.address(8)='1' ELSE histogram_wr_mosi; 
-  common_ram_r_w_rd_mosi_arr(1) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_mosi.address(8)='0' ELSE histogram_rd_mosi;
+  common_ram_r_w_wr_mosi_arr(0) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_ram_pointer='0' ELSE histogram_wr_mosi;
+  common_ram_r_w_rd_mosi_arr(0) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_ram_pointer='0' ELSE histogram_rd_mosi;
+  common_ram_r_w_wr_mosi_arr(1) <= bin_arbiter_wr_mosi WHEN bin_arbiter_wr_ram_pointer='1' ELSE histogram_wr_mosi; 
+  common_ram_r_w_rd_mosi_arr(1) <= bin_arbiter_rd_mosi WHEN bin_arbiter_rd_ram_pointer='1' ELSE histogram_rd_mosi;
 
   -- Let bin_arbiter read RAM 0 while user reads RAM 1 and vice versa
-  bin_arbiter_rd_miso  <= common_ram_r_w_rd_miso_arr(0) WHEN ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1); --FIXME ISSUE: The MISO has 1 cycle more latency than the MOSI (which carries the ram_pointer)
-  histogram_rd_miso    <= common_ram_r_w_rd_miso_arr(1) WHEN ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(0);
+  -- . We always want the MISO bus to switch 1 cycle later than the MOSI (such that the MM operation can finish).
+  bin_arbiter_rd_miso  <= common_ram_r_w_rd_miso_arr(0) WHEN prv_bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(1);
+
+
+--  histogram_rd_miso    <= common_ram_r_w_rd_miso_arr(1) WHEN bin_arbiter_rd_ram_pointer='0' ELSE common_ram_r_w_rd_miso_arr(0);
 
   gen_common_ram_r_w : FOR i IN 0 TO c_nof_common_ram_r_w-1 GENERATE
     u_common_ram_r_w : ENTITY common_lib.common_ram_r_w