Add eth_stream.vhd with test benches.

libraries/io/eth/hdllib.cfg

@@ -22,6 +22,7 @@ synth_files =
     src/vhdl/eth_control.vhd
     src/vhdl/eth_ihl_to_20.vhd
     src/vhdl/eth.vhd
+    src/vhdl/eth_stream.vhd
     src/vhdl/eth_tester_pkg.vhd
     src/vhdl/eth_tester_tx.vhd
     src/vhdl/eth_tester_rx.vhd
@@ -35,8 +36,10 @@ test_bench_files =
     tb/vhdl/tb_eth.vhd
     tb/vhdl/tb_eth_tester_pkg.vhd
     tb/vhdl/tb_eth_tester.vhd
+    tb/vhdl/tb_eth_stream.vhd
     tb/vhdl/tb_tb_eth.vhd
     tb/vhdl/tb_tb_eth_tester.vhd
+    tb/vhdl/tb_tb_eth_stream.vhd
     tb/vhdl/tb_eth_udp_offload.vhd
     tb/vhdl/tb_eth_ihl_to_20.vhd
     tb/vhdl/tb_tb_tb_eth_regression.vhd
@@ -49,6 +52,7 @@ regression_test_vhdl =
     tb/vhdl/tb_eth_ihl_to_20.vhd
     tb/vhdl/tb_tb_eth.vhd
     tb/vhdl/tb_tb_eth_tester.vhd
+    tb/vhdl/tb_tb_eth_stream.vhd
 
 
 [modelsim_project_file]

libraries/io/eth/src/vhdl/eth_stream.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Eric Kooistra
+-- Purpose:
+--   Provide Ethernet access to a node for one UDP stream.
+-- Description:
+-- * This eth_stream.vhd is a stripped down version of eth.vhd.
+-- * This eth_stream only contains the components that are needed to send or
+--   receive an UDP stream via 1GbE.
+--   The IP checksum is filled in for Tx and checked or Rx.
+--   The Tx only contains UDP stream data, so no need for a dp_mux.
+--   The Rx may contain other packet types, because the 1GbE connects to a
+--   network. All Rx packets that are not UDP for g_rx_udp_port are discarded.
+-- References:
+-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.eth_pkg.ALL;
+
+ENTITY eth_stream IS
+  GENERIC (
+    g_rx_udp_port : NATURAL
+  );
+  PORT (
+    -- Clocks and reset
+    st_rst        : IN  STD_LOGIC;
+    st_clk        : IN  STD_LOGIC;
+    
+    -- User UDP interface
+    -- . Tx
+    udp_tx_sosi   : IN  t_dp_sosi;
+    udp_tx_siso   : OUT t_dp_siso;
+    -- . Rx
+    udp_rx_sosi   : OUT t_dp_sosi;
+    udp_rx_siso   : IN  t_dp_siso := c_dp_siso_rdy;
+
+    -- PHY interface
+    -- . Tx
+    tse_tx_sosi   : OUT t_dp_sosi;
+    tse_tx_siso   : IN  t_dp_siso;
+    -- . Rx
+    tse_rx_sosi   : IN  t_dp_sosi;
+    tse_rx_siso   : OUT t_dp_siso
+  );
+END eth_stream;
+
+
+ARCHITECTURE str OF eth_stream IS
+
+  -- ETH Tx
+  SIGNAL eth_tx_siso            : t_dp_siso;
+  SIGNAL eth_tx_sosi            : t_dp_sosi;
+
+  -- ETH Rx
+  SIGNAL rx_adapt_siso          : t_dp_siso;
+  SIGNAL rx_adapt_sosi          : t_dp_sosi;
+  
+  SIGNAL rx_hdr_status          : t_eth_hdr_status;
+  SIGNAL rx_hdr_status_complete : STD_LOGIC;
+
+  SIGNAL rx_eth_discard         : STD_LOGIC;
+  SIGNAL rx_eth_discard_val     : STD_LOGIC;
+
+BEGIN
+
+  ------------------------------------------------------------------------------
+  -- TX
+  ------------------------------------------------------------------------------
+
+  -- Insert IP header checksum
+  u_tx_ip : ENTITY work.eth_hdr
+  GENERIC MAP (
+    g_header_store_and_forward     => TRUE,
+    g_ip_header_checksum_calculate => TRUE
+  )
+  PORT MAP (
+    -- Clocks and reset
+    rst             => st_rst,
+    clk             => st_clk,
+
+    -- Streaming Sink
+    snk_in          => udp_tx_sosi,
+    snk_out         => udp_tx_siso,
+
+    -- Streaming Source
+    src_in          => tse_tx_siso,
+    src_out         => tse_tx_sosi   -- with err field value 0 for OK
+  );
+
+  ------------------------------------------------------------------------------
+  -- RX
+  ------------------------------------------------------------------------------
+
+  -- Adapt the TSE RX source ready latency from 2 to 1
+  u_adapt : ENTITY dp_lib.dp_latency_adapter
+  GENERIC MAP (
+    g_in_latency  => c_eth_rx_ready_latency,  -- = 2
+    g_out_latency => c_eth_ready_latency      -- = 1
+  )
+  PORT MAP (
+    rst     => st_rst,
+    clk     => st_clk,
+    -- ST sink
+    snk_out => tse_rx_siso,
+    snk_in  => tse_rx_sosi,
+    -- ST source
+    src_in  => rx_adapt_siso,
+    src_out => rx_adapt_sosi
+  );
+  
+  -- Pass on UDP stream for g_rx_udp_port
+  -- . Verify IP header checksum for IP
+  u_rx_udp : ENTITY work.eth_hdr
+  GENERIC MAP (
+    g_header_store_and_forward     => TRUE,
+    g_ip_header_checksum_calculate => TRUE
+  )
+  PORT MAP (
+    -- Clocks and reset
+    rst             => st_rst,
+    clk             => st_clk,
+    
+    -- Streaming Sink
+    snk_in          => rx_adapt_sosi,
+    snk_out         => rx_adapt_siso,
+    
+    -- Streaming Source
+    src_in          => udp_rx_siso,
+    src_out         => udp_rx_sosi,
+
+    -- Frame control
+    frm_discard     => rx_eth_discard,
+    frm_discard_val => rx_eth_discard_val,
+    
+    -- Header info
+    hdr_status          => rx_hdr_status,
+    hdr_status_complete => rx_hdr_status_complete
+  );
+
+  -- Discard all Rx data that is not UDP for g_rx_udp_port
+  p_rx_discard : PROCESS(st_rst, st_clk)
+  BEGIN
+    IF st_rst = '1' THEN
+      rx_eth_discard <= '1';  -- default discard
+      rx_eth_discard_val <= '0';
+    ELSIF rising_edge(st_clk) THEN
+      -- Default keep rx_eth_discard status (instead of '1'), to more clearly
+      -- see when a change occurs
+      IF rx_hdr_status_complete = '1' THEN
+        rx_eth_discard <= '1';  -- default discard
+        IF rx_hdr_status.is_ip = '1' AND
+           rx_hdr_status.is_udp = '1' AND
+           TO_UINT(rx_hdr_status.udp_port) = g_rx_udp_port THEN
+          rx_eth_discard <= '0';  -- pass on IP/UDP stream for g_rx_udp_port
+        END IF;
+      END IF;
+
+      rx_eth_discard_val <= rx_hdr_status_complete;
+    END IF;
+  END PROCESS;
+
+END str;

libraries/io/eth/tb/vhdl/tb_tb_eth_stream.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: E. Kooistra
+-- Purpose: Multi test bench for eth_stream
+-- Description:
+--
+-- Usage:
+--   > as 8
+--   > run -all
+
+LIBRARY IEEE, diag_lib;
+USE IEEE.std_logic_1164.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.tb_eth_tester_pkg.ALL;
+
+ENTITY tb_tb_eth_stream IS
+END tb_tb_eth_stream;
+
+ARCHITECTURE tb OF tb_tb_eth_stream IS
+
+  -- Tb
+  CONSTANT c_eth_clk_MHz   : NATURAL := 125;
+  CONSTANT c_st_clk_MHz    : NATURAL := 200;
+  CONSTANT c_nof_sync      : NATURAL := 2;
+  CONSTANT c_nof_blk       : NATURAL := 3;   -- nof_blk per sync
+
+  -- Tx packet size and gap size in octets
+  CONSTANT c_block_len     : NATURAL := 50;
+  CONSTANT c_link_len      : NATURAL := func_eth_tester_eth_packet_on_link_length(c_block_len);
+
+  -- For near maximum 1Gbps link rate the c_block_len + c_gap_len_min time
+  -- in the st_clk domain equals c_link_len time in eth_clk domain.
+  CONSTANT c_gap_len_min   : NATURAL := c_link_len * c_st_clk_MHz / c_eth_clk_MHz - c_block_len;
+
+  -- Choose c_gap_len somewhat larger to have packet link rate < 1 Gbps
+  CONSTANT c_gap_len       : NATURAL := c_gap_len_min * 2;   -- for g_nof_streams = 1
+
+  -- BG ctrl
+  CONSTANT c_high          : NATURAL := c_diag_bg_mem_max_adr;  -- = 2**24
+
+  CONSTANT c_bg_ctrl       : t_diag_block_gen_integer := ('1', '1', c_block_len,  c_nof_blk, c_gap_len, 0, c_high, 0);  -- for first stream
+
+BEGIN
+
+--  g_tb_index         : NATURAL := 0;  -- use to incremental delay logging from tb instances in tb_tb
+--  g_nof_sync         : NATURAL := 2;  -- number of BG sync intervals to set c_run_time
+--  g_udp_port_match   : BOOLEAN := TRUE;
+--
+--  -- t_diag_block_gen_integer =
+--  --   sl:  enable
+--  --   sl:  enable_sync
+--  --   nat: samples_per_packet
+--  --   nat: blocks_per_sync
+--  --   nat: gapsize
+--  --   nat: mem_low_adrs
+--  --   nat: mem_high_adrs
+--  --   nat: bsn_init
+--  g_bg_ctrl    : t_diag_block_gen_integer := ('1', '1', 50, 3, 200, 0, c_diag_bg_mem_max_adr, 0)  -- for first stream
+
+  u_udp          : ENTITY work.tb_eth_stream GENERIC MAP (0, c_nof_sync,  TRUE, c_bg_ctrl);
+  u_udp_mismatch : ENTITY work.tb_eth_stream GENERIC MAP (1, c_nof_sync, FALSE, c_bg_ctrl);
+
+END tb;