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Commit 57034f10 authored by Eric Kooistra's avatar Eric Kooistra
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Corrected sim_ddr model, tb_io_ddr now passes with g_sim_model = true.

parent b5f9f27f
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libraries/technology/ddr/sim_ddr.vhd
+ 109
− 59
View file @ 57034f10
...@@ -69,9 +69,18 @@ ARCHITECTURE str OF sim_ddr IS ...@@ -69,9 +69,18 @@ ARCHITECTURE str OF sim_ddr IS
SIGNAL sim_clk : STD_LOGIC; SIGNAL sim_clk : STD_LOGIC;
SIGNAL sim_rst : STD_LOGIC; SIGNAL sim_rst : STD_LOGIC;
SIGNAL sim_ctlr_mosi : t_mem_ctlr_mosi;
SIGNAL address : NATURAL; SIGNAL address : NATURAL;
SIGNAL burst_size : NATURAL;
SIGNAL burst_cnt : NATURAL;
SIGNAL waitrequest_n : STD_LOGIC := '1';
SIGNAL wr_bursting : BOOLEAN := FALSE;
SIGNAL rd_bursting : BOOLEAN := FALSE;
SIGNAL pending_wr : BOOLEAN := FALSE;
SIGNAL pending_rd : BOOLEAN := FALSE;
SIGNAL pending_address : NATURAL;
SIGNAL pending_burst_size : NATURAL;
BEGIN BEGIN
...@@ -85,72 +94,113 @@ BEGIN ...@@ -85,72 +94,113 @@ BEGIN
ctlr_miso.cal_ok <= '0' , '1' AFTER 1 ns; ctlr_miso.cal_ok <= '0' , '1' AFTER 1 ns;
ctlr_miso.cal_fail <= '0'; ctlr_miso.cal_fail <= '0';
-- Delay the control one cycle here so p_mem_access can update its outputs immediately ctlr_miso.waitrequest_n <= waitrequest_n;
p_clk : PROCESS(sim_clk)
BEGIN
IF rising_edge(sim_clk) THEN
sim_ctlr_mosi <= ctlr_mosi;
END IF;
END PROCESS;
p_mem_access : PROCESS(sim_clk, sim_ctlr_mosi) p_mem_access : PROCESS(sim_clk)
VARIABLE v_enable_model : BOOLEAN := FALSE; -- Process variables get initalized once and then they keep their state
VARIABLE v_mem_arr : t_mem_arr := (OTHERS=>(OTHERS=>'0')); VARIABLE v_mem_arr : t_mem_arr := (OTHERS=>(OTHERS=>'0'));
VARIABLE v_address : NATURAL := 0;
VARIABLE v_address : NATURAL;
VARIABLE v_burst_size : NATURAL;
VARIABLE v_burst_cnt : NATURAL := 0;
VARIABLE v_wr_bursting : BOOLEAN := FALSE; VARIABLE v_wr_bursting : BOOLEAN := FALSE;
VARIABLE v_rd_bursting : BOOLEAN := FALSE; VARIABLE v_rd_bursting : BOOLEAN := FALSE;
VARIABLE v_burst_cnt : NATURAL := 0; VARIABLE v_waitrequest_n : STD_LOGIC := '1';
VARIABLE v_burst_size : NATURAL := 0;
BEGIN
-- Don't waste simulation time when user does not access the model anyway BEGIN
IF v_enable_model = FALSE THEN
ctlr_miso.waitrequest_n <= '1';
IF sim_ctlr_mosi.burstbegin='1' THEN
v_enable_model := TRUE;
END IF;
END IF;
IF v_enable_model = TRUE THEN
IF rising_edge(sim_clk) THEN IF rising_edge(sim_clk) THEN
ctlr_miso.rdval <= '0'; -- Get state
ctlr_miso.waitrequest_n <= '1'; --v_address := address;
--v_burst_size := burst_size;
-- Access: burst begin --v_burst_cnt := burst_cnt;
IF sim_ctlr_mosi.burstbegin='1' THEN --v_waitrequest_n := waitrequest_n;
IF sim_ctlr_mosi.wr='1' THEN --v_wr_bursting := wr_bursting;
--v_rd_bursting := rd_bursting;
-- Burst begin
IF ctlr_mosi.burstbegin='1' THEN
IF ctlr_mosi.wr='1' THEN
IF v_rd_bursting=FALSE THEN
v_wr_bursting := TRUE; v_wr_bursting := TRUE;
ELSIF sim_ctlr_mosi.rd='1' THEN v_address := TO_UINT(ctlr_mosi.address);
v_burst_size := TO_UINT(ctlr_mosi.burstsize);
v_burst_cnt := 0;
ELSE
pending_wr <= TRUE;
pending_address <= TO_UINT(ctlr_mosi.address);
pending_burst_size <= TO_UINT(ctlr_mosi.burstsize);
END IF;
ELSIF ctlr_mosi.rd='1' THEN
IF v_rd_bursting=FALSE THEN
v_rd_bursting := TRUE; v_rd_bursting := TRUE;
v_waitrequest_n := '0';
v_address := TO_UINT(ctlr_mosi.address);
v_burst_size := TO_UINT(ctlr_mosi.burstsize);
v_burst_cnt := 0;
ELSE
pending_rd <= TRUE;
pending_address <= TO_UINT(ctlr_mosi.address);
pending_burst_size <= TO_UINT(ctlr_mosi.burstsize);
END IF;
END IF;
END IF;
-- Pending write burst begin, after read burst
IF pending_wr=TRUE AND v_rd_bursting=FALSE THEN
pending_wr <= FALSE;
IF ctlr_mosi.wr='1' THEN -- require that user has kept wr still active
v_wr_bursting := TRUE;
v_address := pending_address;
v_burst_size := pending_burst_size;
v_burst_cnt := 0;
END IF;
END IF; END IF;
v_address := TO_UINT(sim_ctlr_mosi.address);
v_burst_size := TO_UINT(sim_ctlr_mosi.burstsize); -- Pending read burst begin, after read burst
IF pending_rd=TRUE AND v_rd_bursting=FALSE THEN
pending_rd <= FALSE;
IF ctlr_mosi.rd='1' THEN -- require that user has kept rd still active
v_rd_bursting := TRUE;
v_address := pending_address;
v_burst_size := pending_burst_size;
v_burst_cnt := 0; v_burst_cnt := 0;
v_waitrequest_n := '0';
END IF;
END IF; END IF;
IF v_wr_bursting=TRUE OR v_rd_bursting=TRUE THEN -- Write access
IF sim_ctlr_mosi.wr='1' THEN -- Write IF v_wr_bursting=TRUE AND ctlr_mosi.wr='1' THEN
v_mem_arr(v_address) := sim_ctlr_mosi.wrdata(c_dat_w-1 DOWNTO 0); v_mem_arr(v_address) := ctlr_mosi.wrdata(c_dat_w-1 DOWNTO 0);
v_address := v_address + 1; v_address := v_address + 1;
v_burst_cnt := v_burst_cnt + 1; v_burst_cnt := v_burst_cnt + 1;
ELSIF v_rd_bursting=TRUE THEN -- Read END IF;
-- Read access
ctlr_miso.rdval <= '0';
IF v_rd_bursting=TRUE THEN
ctlr_miso.rddata(c_dat_w-1 DOWNTO 0) <= v_mem_arr(v_address); ctlr_miso.rddata(c_dat_w-1 DOWNTO 0) <= v_mem_arr(v_address);
ctlr_miso.rdval <= '1'; ctlr_miso.rdval <= '1';
ctlr_miso.waitrequest_n <= '0';
v_address := v_address + 1; v_address := v_address + 1;
v_burst_cnt := v_burst_cnt + 1; v_burst_cnt := v_burst_cnt + 1;
END IF; END IF;
-- Burst size count
IF v_burst_cnt = v_burst_size THEN IF v_burst_cnt = v_burst_size THEN
v_wr_bursting := FALSE; v_wr_bursting := FALSE;
v_rd_bursting := FALSE; v_rd_bursting := FALSE;
END IF; v_waitrequest_n := '1';
END IF; END IF;
address <= v_address; -- Show state
--address <= v_address;
--burst_size <= v_burst_size;
--burst_cnt <= v_burst_cnt;
--wr_bursting <= v_wr_bursting;
--rd_bursting <= v_rd_bursting;
END IF; waitrequest_n <= v_waitrequest_n;
END IF; END IF;
END PROCESS; END PROCESS;
......
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