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Commit 561cfcb0 authored by Eric Kooistra's avatar Eric Kooistra
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Removed in_sync. Use NEGATE_SVEC().

parent 32ea0cc6
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1 merge request!205Added g_sepa_switch_en to support mitigation of quantization noise crosstalk...
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libraries/dsp/fft/src/vhdl/fft_switch.vhd
+ 50
− 48
View file @ 561cfcb0
......@@ -20,15 +20,25 @@
--
-- Author: ported by E. Kooistra, original 2004 by W. Lubberhuizen / W. Poeisz
-- Purpose: Scramble quantization noise crosstalk between two real inputs
-- Description: Ported from LOFAR1, see readme_lofar1.txt
-- Description:
-- . Ported from LOFAR1, see readme_lofar1.txt
-- . Removed in_sync, because the in_val are guaranteed to arrive in blocks of
-- c_nof_clk_per_block samples, forever after rst release.
-- The purpose of the in_sync is to recover from an fractional input block,
-- but that cannot occur. The other parts of the FFT also rely on this block
-- processing, without need for in_sync to recover from fractional blocks.
-- The application that uses the FFT must guarantee to only pass on complete
-- blocks of c_nof_clk_per_block samples to the FFT.
-- Remark: Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
LIBRARY IEEE;
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY fft_switch IS
GENERIC (
g_nof_clk_per_sync : NATURAL := 200*10**6;
g_fft_sz_w : NATURAL;
g_dat_w : NATURAL
);
......@@ -36,12 +46,10 @@ ENTITY fft_switch IS
in_re : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
in_im : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
in_val : IN STD_LOGIC;
in_sync : IN STD_LOGIC;
switch_en : IN STD_LOGIC;
switch_en : IN STD_LOGIC := '1';
out_re : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
out_im : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
out_val : OUT STD_LOGIC;
out_sync : OUT STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
......@@ -50,6 +58,8 @@ END fft_switch;
ARCHITECTURE rtl OF fft_switch IS
CONSTANT c_nof_clk_per_block : NATURAL := 2**g_fft_sz_w;
SIGNAL cnt : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0);
SIGNAL nxt_cnt : STD_LOGIC_VECTOR(cnt'RANGE);
......@@ -58,7 +68,6 @@ ARCHITECTURE rtl OF fft_switch IS
SIGNAL lfsr_en : STD_LOGIC;
SIGNAL nxt_out_val : STD_LOGIC;
SIGNAL nxt_out_sync : STD_LOGIC;
SIGNAL nxt_out_re : STD_LOGIC_VECTOR(in_re'RANGE);
SIGNAL nxt_out_im : STD_LOGIC_VECTOR(in_im'RANGE);
......@@ -69,52 +78,45 @@ BEGIN
IF rst = '1' THEN
cnt <= (OTHERS => '0');
out_val <= '0';
out_sync <= '0';
out_re <= (OTHERS => '0');
out_im <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
cnt <= nxt_cnt;
out_val <= nxt_out_val;
out_val <= in_val;
out_re <= nxt_out_re;
out_im <= nxt_out_im;
out_sync <= nxt_out_sync;
END IF;
END PROCESS;
p_counter: PROCESS(cnt, in_val, in_sync)
p_counter: PROCESS(cnt, in_val)
BEGIN
nxt_cnt <= cnt;
IF in_sync='1' THEN
nxt_cnt <= (OTHERS => '0');
ELSIF in_val='1' THEN
nxt_cnt <= STD_LOGIC_VECTOR(UNSIGNED(cnt)+1);
IF in_val = '1' THEN
nxt_cnt <= INCR_UVEC(cnt, 1);
END IF;
END PROCESS;
p_lfsr_ctrl: PROCESS(cnt, in_val)
BEGIN
if SIGNED(cnt)=-1 AND in_val='1' THEN
if TO_SINT(cnt) = -1 AND in_val = '1' THEN
lfsr_en <= '1';
ELSE
lfsr_en <= '0';
END IF;
END PROCESS;
p_out: PROCESS(cnt, lfsr_bit1, lfsr_bit2, in_im, in_re, in_val, in_sync, switch_en)
p_out: PROCESS(in_re, in_im, switch_en, cnt, lfsr_bit1, lfsr_bit2)
BEGIN
nxt_out_val <= in_val;
nxt_out_sync <= in_sync AND in_val;
IF lfsr_bit1=cnt(cnt'HIGH) AND switch_en='1' THEN
nxt_out_re <= STD_LOGIC_VECTOR(-SIGNED(in_re));
ELSE
nxt_out_re <= in_re;
END IF;
IF lfsr_bit2=cnt(cnt'HIGH) AND switch_en='1' THEN
nxt_out_im <= STD_LOGIC_VECTOR(-SIGNED(in_im));
ELSE
nxt_out_im <= in_im;
IF switch_en = '1' THEN
IF lfsr_bit1 = cnt(cnt'HIGH) THEN
nxt_out_re <= NEGATE_SVEC(in_re);
END IF;
IF lfsr_bit2 = cnt(cnt'HIGH) THEN
nxt_out_im <= NEGATE_SVEC(in_im);
END IF;
END IF;
END PROCESS;
......
libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
+ 47
− 45
View file @ 561cfcb0
......@@ -20,15 +20,20 @@
--
-- Author: ported by E. Kooistra, original 2004 by W. Lubberhuizen / W. Poeisz
-- Purpose: Scramble quantization noise crosstalk between two real inputs
-- Description: Ported from LOFAR1, see readme_lofar1.txt
-- Description:
-- . Ported from LOFAR1, see readme_lofar1.txt
-- . Removed in_sync, because the in_val are guaranteed to arrive in blocks of
-- c_nof_clk_per_block samples, forever after rst release.
-- Remark: Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY fft_unswitch IS
GENERIC (
g_nof_clk_per_sync : NATURAL := 200*10**6;
g_fft_sz_w : NATURAL;
g_dat_w : NATURAL
);
......@@ -36,12 +41,10 @@ ENTITY fft_unswitch IS
in_re : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
in_im : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
in_val : IN STD_LOGIC;
in_sync : IN STD_LOGIC;
switch_en : IN STD_LOGIC;
switch_en : IN STD_LOGIC := '1';
out_re : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
out_im : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
out_val : OUT STD_LOGIC;
out_sync : OUT STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
......@@ -49,6 +52,10 @@ END fft_unswitch;
ARCHITECTURE rtl OF fft_unswitch IS
CONSTANT c_nof_clk_per_block : NATURAL := 2**g_fft_sz_w;
SIGNAL in_sosi : t_dp_sosi;
SIGNAL cnt : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0);
SIGNAL nxt_cnt : STD_LOGIC_VECTOR(cnt'RANGE);
......@@ -58,7 +65,6 @@ ARCHITECTURE rtl OF fft_unswitch IS
SIGNAL lfsr_en : STD_LOGIC;
SIGNAL nxt_out_val : STD_LOGIC;
SIGNAL nxt_out_sync : STD_LOGIC;
SIGNAL nxt_out_re : STD_LOGIC_VECTOR(in_re'RANGE);
SIGNAL nxt_out_im : STD_LOGIC_VECTOR(in_im'RANGE);
......@@ -69,47 +75,44 @@ BEGIN
IF rst = '1' THEN
cnt <= (OTHERS => '0');
out_val <= '0';
out_sync <= '0';
out_re <= (OTHERS => '0');
out_im <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
cnt <= nxt_cnt;
out_val <= nxt_out_val;
out_sync <= nxt_out_sync;
out_val <= in_val;
out_re <= nxt_out_re;
out_im <= nxt_out_im;
END IF;
END PROCESS;
p_counter: PROCESS(cnt, in_val, in_sync)
p_counter: PROCESS(cnt, in_val)
BEGIN
nxt_cnt <= cnt;
IF in_sync='1' THEN
nxt_cnt <= (OTHERS => '0');
ELSIF in_val='1' THEN
nxt_cnt <= STD_LOGIC_VECTOR(UNSIGNED(cnt)+1);
IF in_val = '1' THEN
nxt_cnt <= INCR_UVEC(cnt, 1);
END IF;
END PROCESS;
p_lfsr_ctrl: PROCESS(cnt, in_val)
BEGIN
if SIGNED(cnt)=-1 AND in_val='1' THEN
if TO_SINT(cnt) = -1 AND in_val = '1' THEN
lfsr_en <= '1';
ELSE
lfsr_en <= '0';
END IF;
END PROCESS;
p_out: PROCESS(in_re, in_im, in_val, in_sync, cnt, lfsr_bit1, lfsr_bit2, switch_en)
p_out: PROCESS(in_re, in_im, switch_en, cnt, lfsr_bit1, lfsr_bit2)
BEGIN
nxt_out_val <= in_val;
nxt_out_sync <= in_sync AND in_val;
nxt_out_re <= in_re;
nxt_out_im <= in_im;
IF ((cnt(0)='0' AND cnt(cnt'HIGH)=lfsr_bit1)
OR (cnt(0)='1' AND cnt(cnt'HIGH)=lfsr_bit2)) AND (switch_en='1') THEN
nxt_out_re <= STD_LOGIC_VECTOR(-SIGNED(in_re));
nxt_out_im <= STD_LOGIC_VECTOR(-SIGNED(in_im));
IF switch_en = '1' THEN
IF (cnt(0) = '0' AND cnt(cnt'HIGH) = lfsr_bit1) OR
(cnt(0) = '1' AND cnt(cnt'HIGH) = lfsr_bit2) THEN
nxt_out_re <= NEGATE_SVEC(in_re);
nxt_out_im <= NEGATE_SVEC(in_im);
END IF;
END IF;
END PROCESS;
......@@ -123,4 +126,3 @@ BEGIN
);
END rtl;
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