Removed unnecessary () in if then statements. Added r.ctrl_reg to capture the...

Removed unnecessary () in if then statements. Added r.ctrl_reg to capture the control only at the end of aBG period orwhenidle.

libraries/base/diag/src/vhdl/diag_block_gen.vhd

@@ -53,6 +53,7 @@ architecture rtl of diag_block_gen is
   type state_type is (s_idle, s_block, s_gap);
 
   type reg_type is record
+    ctrl_reg    : t_diag_block_gen;  -- capture ctrl
     blk_en      : std_logic;  -- enable at block level
     blk_xon     : std_logic;  -- siso.xon at block level, the BG continues but the sosi control depend on xon (the BG does not support siso.ready)
     blk_sync    : std_logic;  -- block sync alternative of the pulse sync
@@ -82,11 +83,11 @@ begin
       variable v_mem_high_adrs      : natural;
     begin
     
-      v_samples_per_packet := TO_UINT(ctrl.samples_per_packet);
-      v_gapsize            := TO_UINT(ctrl.gapsize);
-      v_blocks_per_sync    := TO_UINT(ctrl.blocks_per_sync); 
-      v_mem_low_adrs       := TO_UINT(ctrl.mem_low_adrs); 
-      v_mem_high_adrs      := TO_UINT(ctrl.mem_high_adrs);
+      v_samples_per_packet := TO_UINT(r.ctrl_reg.samples_per_packet);
+      v_gapsize            := TO_UINT(r.ctrl_reg.gapsize);
+      v_blocks_per_sync    := TO_UINT(r.ctrl_reg.blocks_per_sync); 
+      v_mem_low_adrs       := TO_UINT(r.ctrl_reg.mem_low_adrs); 
+      v_mem_high_adrs      := TO_UINT(r.ctrl_reg.mem_high_adrs);
       
       v                   := r;     -- default hold all r fields
       v.pls_sync          := '0';
@@ -116,36 +117,39 @@ begin
       
       case r.state is
         when s_idle => 
+          v.ctrl_reg    := ctrl;        -- accept new control settings
           v.blk_xon     := out_siso.xon;
           v.blk_sync    := '0';
           v.samples_cnt := 0;
           v.blocks_cnt  := 0;    
           v.bsn_cnt     := ctrl.bsn_init;
           v.mem_cnt     := v_mem_low_adrs; 
-          if(r.blk_en = '1') then       -- Wait until enabled
+          if r.blk_en = '1' then       -- Wait until enabled
             v.rd_ena      := '1';
             v.state       := s_block;        
           end if;
           
         when s_block =>
           v.rd_ena := '1';
-          if(r.samples_cnt = 0 and r.blocks_cnt = 0) then 
+          if r.samples_cnt = 0 and r.blocks_cnt = 0 then 
             v.pls_sync    := '1';                      -- Always start with a pulse sync          
             v.blk_sync    := '1';
             v.sop         := '1';
             v.samples_cnt := v.samples_cnt + 1; 
-          elsif(r.samples_cnt = 0) then
+          elsif r.samples_cnt = 0 then
             v.sop         := '1';
             v.samples_cnt := v.samples_cnt + 1; 
-          elsif(r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync-1) then 
+          elsif r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync-1 then 
             v.eop         := '1'; 
+            v.ctrl_reg    := ctrl;      -- accept new control settings at end of block when gapsize=0
             v.samples_cnt := 0; 
             v.blocks_cnt  := 0;
-          elsif(r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0) then 
+          elsif r.samples_cnt >= v_samples_per_packet-1 and v_gapsize = 0 then 
             v.eop         := '1'; 
+            v.ctrl_reg    := ctrl;      -- accept new control settings at end of block when gapsize=0
             v.samples_cnt := 0; 
             v.blocks_cnt  := r.blocks_cnt + 1;
-          elsif(r.samples_cnt >= v_samples_per_packet-1) then 
+          elsif r.samples_cnt >= v_samples_per_packet-1 then 
             v.eop         := '1'; 
             v.samples_cnt := 0; 
             v.rd_ena      := '0';
@@ -155,26 +159,28 @@ begin
           end if;
           v.valid  := '1';
           
-          if(r.mem_cnt >= v_mem_high_adrs) then 
+          if r.mem_cnt >= v_mem_high_adrs then 
             v.mem_cnt := v_mem_low_adrs;
           else
             v.mem_cnt := r.mem_cnt + 1;
           end if; 
           
-          if(v.eop = '1' and r.blk_en = '0') then
+          if v.eop = '1' and r.blk_en = '0' then
             v.state := s_idle;          -- accept disable after eop, not during block
           end if;
-          if(r.eop = '1') then
+          if r.eop = '1' then
             v.blk_xon := out_siso.xon;  -- accept XOFF after eop, not during block
           end if;
 
         when s_gap => 
-          if(r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync-1) then 
+          if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync-1 then 
+            v.ctrl_reg    := ctrl;      -- accept new control settings at end of gap
             v.samples_cnt := 0; 
             v.blocks_cnt  := 0;
             v.rd_ena      := '1';
             v.state       := s_block;
-          elsif(r.samples_cnt >= v_gapsize-1) then 
+          elsif r.samples_cnt >= v_gapsize-1 then 
+            v.ctrl_reg    := ctrl;      -- accept new control settings at end of gap
             v.samples_cnt := 0;             
             v.blocks_cnt  := r.blocks_cnt + 1;
             v.rd_ena      := '1';
@@ -183,7 +189,7 @@ begin
             v.samples_cnt := r.samples_cnt + 1;
           end if; 
           
-          if(r.blk_en = '0') then
+          if r.blk_en = '0' then
             v.state := s_idle;
           end if;
           v.blk_xon := out_siso.xon;
@@ -193,7 +199,8 @@ begin
 
       end case;
       
-      if(rst = '1') then 
+      if rst = '1' then 
+        v.ctrl_reg    := c_diag_block_gen_rst; 
         v.blk_en      := '0'; 
         v.blk_xon     := '0'; 
         v.blk_sync    := '0';