Define g_tech_ddr as generic.

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -25,7 +25,7 @@
 --                        - uphy_4g_800_master
 --                        - uphy_4g_800_slave
 --
--- The DUT can be selected, using the c_tech_ddr constants. 
+-- The DUT can be selected, using the g_tech_ddr constants. 
 --
 -- Testbench is selftesting: 
 --
@@ -47,11 +47,13 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
 ENTITY tb_io_ddr IS
   GENERIC (
     g_technology            : NATURAL := c_tech_select_default;
+    g_tech_ddr              : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+    --g_tech_ddr              : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
     g_sim                   : BOOLEAN := TRUE;  -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
     g_ctlr_ref_clk_period   : TIME := 5 ns;     -- 200 MHz
     g_dvr_clk_period        : TIME := 5 ns;     -- 50 ns
     g_dp_clk_period         : TIME := 5000 ps;  -- 200 MHz
-    g_dp_data_w             : NATURAL := 32;    -- 32 for mixed width and 256 for equal width FIFO
+    g_dp_data_w             : NATURAL := 256;    -- 32 for mixed width and 256 for equal width FIFO
     g_nof_repeat            : NATURAL := 2;
     g_wr_flush_mode         : STRING := "SYN"  -- "VAL", "SOP", "SYN"
   );
@@ -61,18 +63,19 @@ ARCHITECTURE str of tb_io_ddr IS
 
   CONSTANT c_cross_domain_dvr_ctlr : BOOLEAN := g_ctlr_ref_clk_period/=g_dvr_clk_period;
 
-  CONSTANT c_tech_ddr         : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-  
-  CONSTANT c_ctlr_address_w   : NATURAL := func_tech_ddr_ctlr_address_w(c_tech_ddr);
-  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr);
+  CONSTANT c_ctlr_address_w   : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
+  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr);
   
   -- DDR access stimuli
-  -- . write 517 and 507 words and then read back these 1024, to verify that 2 block writes can be readback in 1 block read
+  -- . write the words in two parts and the read back all these, to verify that 2 block writes can be readback in 1 block read
   -- . write 1 + 6 words and then readback the 1+1+2+3 = 7 words, in between also write 0 and read back 0 words (to verify that these are indeed void)
   -- . write 1900 words and read back to verify an access can span more than one DDR address column (a_col_w=10).
-  CONSTANT c_ctlr_address_lo_arr   : t_nat_natural_arr := (  0, 517,    0,     1,   2,    1,   1,    1,   2,   3,   5,  1900, 1900);
-  CONSTANT c_ctlr_nof_address_arr  : t_nat_natural_arr := (517, 507, 1024,     1,   6,    0,   0,    1,   1,   2,   3,   153,  153);
-  CONSTANT c_ctlr_wr_not_rd_arr    : STD_LOGIC_VECTOR  := ('1', '1',  '0',   '1', '1',  '1', '0',  '0', '0', '0', '0',    '1', '0');
+  CONSTANT c_all                   : NATURAL := 3017;
+  CONSTANT c_part                  : NATURAL := c_all/2;
+  CONSTANT c_rest                  : NATURAL := c_all-c_part;
+  CONSTANT c_ctlr_address_lo_arr   : t_nat_natural_arr := (     0, c_part,     0,     1,   2,    1,   1,    1,   2,   3,   5,  1900, 1900);
+  CONSTANT c_ctlr_nof_address_arr  : t_nat_natural_arr := (c_part, c_rest, c_all,     1,   6,    0,   0,    1,   1,   2,   3,   153,  153);
+  CONSTANT c_ctlr_wr_not_rd_arr    : STD_LOGIC_VECTOR  := (   '1',    '1',   '0',   '1', '1',  '1', '0',  '0', '0', '0', '0',    '1', '0');
                                                     
   CONSTANT c_dp_factor        : NATURAL := c_ctlr_data_w/g_dp_data_w;
   
@@ -159,7 +162,7 @@ BEGIN
     snk_diag_en <= '1';
     
     -- After reset the write FIFO is flushed until the first write access is started, even when dvr_wr_flush_en='0'
-    proc_common_wait_some_cycles(ctlr_clk, 100);
+    proc_common_wait_some_cycles(ctlr_clk, 1000);
     
     FOR R IN 0 TO g_nof_repeat-1 LOOP
       FOR I IN c_ctlr_address_lo_arr'RANGE LOOP
@@ -271,7 +274,7 @@ BEGIN
   u_io_ddr: ENTITY work.io_ddr
   GENERIC MAP(
     g_technology             => g_technology,
-    g_tech_ddr               => c_tech_ddr,
+    g_tech_ddr               => g_tech_ddr,
     g_sim                    => g_sim,            -- when TRUE use internal DDR memory model
     g_cross_domain_dvr_ctlr  => c_cross_domain_dvr_ctlr,
     g_wr_data_w              => g_dp_data_w,
@@ -327,7 +330,7 @@ BEGIN
   external_ddr_memory_model : IF g_sim=FALSE GENERATE
     u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
     GENERIC MAP (
-      g_tech_ddr => c_tech_ddr
+      g_tech_ddr => g_tech_ddr
     )
     PORT MAP (
       mem_in => phy_ou,

libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd

@@ -25,10 +25,11 @@
 --   > as 5
 --   > run -all
 
-LIBRARY IEEE, technology_lib;
+LIBRARY IEEE, technology_lib, tech_ddr_lib;
 USE IEEE.std_logic_1164.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
 
 
 ENTITY tb_tb_io_ddr IS
@@ -37,9 +38,13 @@ END tb_tb_io_ddr;
 
 ARCHITECTURE tb OF tb_tb_io_ddr IS
 
+  CONSTANT c_technology     : NATURAL      := c_tech_select_default;
+  CONSTANT c_tech_ddr       : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+  
 BEGIN
 
   -- g_technology           : NATURAL := c_tech_select_default;
+  -- g_tech_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
   -- g_sim                  : BOOLEAN := TRUE;  -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
   -- g_ctlr_ref_clk_period  : TIME := 5 ns;     -- 200 MHz
   -- g_dvr_clk_period       : TIME := 20 ns;    -- 50 ns
@@ -48,14 +53,14 @@ BEGIN
   -- g_nof_repeat           : NATURAL := 2;
   -- g_wr_flush_mode        : STRING := "SYN"  -- "VAL", "SOP", "SYN"
 
-  u_fill_wrfifo_on_next_valid     : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "VAL");
-  u_fill_wrfifo_on_next_sop       : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "SOP");
-  u_fill_wrfifo_on_next_sync      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "SYN");
+  u_fill_wrfifo_on_next_valid     : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "VAL");
+  u_fill_wrfifo_on_next_sop       : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "SOP");
+  u_fill_wrfifo_on_next_sync      : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "SYN");
   
-  u_ext_memory_model              : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default,  TRUE, 5 ns,  5 ns, 5 ns, 256, 1, "VAL");
-  u_mixed_width                   : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns,  32, 1, "VAL");
+  u_ext_memory_model              : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr,  TRUE, 5 ns,  5 ns, 5 ns, 256, 1, "VAL");
+  u_mixed_width                   : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr, FALSE, 5 ns,  5 ns, 5 ns,  32, 1, "VAL");
   
-  u_cross_dvr_to_faster_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns, 20 ns, 5 ns, 256, 1, "VAL");
-  u_cross_dvr_to_slower_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  1 ns, 5 ns, 256, 1, "VAL");
+  u_cross_dvr_to_faster_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr, FALSE, 5 ns, 20 ns, 5 ns, 256, 1, "VAL");
+  u_cross_dvr_to_slower_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr, FALSE, 5 ns,  1 ns, 5 ns, 256, 1, "VAL");
   
 END tb;