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Commit 55314038 authored by Reinier van der Walle's avatar Reinier van der Walle
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updated mmap gold files

parent 50f0a50d
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1 merge request!251Resolve L2SDP-721
Pipeline #29895 passed
......@@ -34,7 +34,7 @@ number_of_columns = 13
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
- - - - design_note 0x00008014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
......@@ -542,7 +542,7 @@ number_of_columns = 13
- - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
......@@ -551,7 +551,7 @@ number_of_columns = 13
- - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
- - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
......
......@@ -34,7 +34,7 @@ number_of_columns = 13
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
- - - - design_note 0x00008014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
......@@ -542,7 +542,7 @@ number_of_columns = 13
- - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
......@@ -551,7 +551,7 @@ number_of_columns = 13
- - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
- - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
......
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