Tb now compiles and loads oke in simulation.

applications/apertif/designs/apertif_unb1_fn_beamformer/tb/vhdl/tb_apertif_unb1_fn_beamformer.vhd

@@ -77,15 +77,7 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_beamformer IS
   SIGNAL si_fn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
   SIGNAL fn_bn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
   
-  -- Signals to interface with the DDR3 memory model.
-  SIGNAL phy_in              : t_tech_ddr3_phy_in_arr(0 DOWNTO 0);
-  SIGNAL phy_io              : t_tech_ddr3_phy_io_arr(0 DOWNTO 0);
-  SIGNAL phy_ou              : t_tech_ddr3_phy_ou_arr(0 DOWNTO 0);   
-  
-  SIGNAL ras_n               : STD_LOGIC_VECTOR(0 DOWNTO 0);
-  SIGNAL cas_n               : STD_LOGIC_VECTOR(0 DOWNTO 0);
-  SIGNAL we_n                : STD_LOGIC_VECTOR(0 DOWNTO 0);
-
+  SIGNAL phy_in_x            : t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;  -- use internal DDR3 model instead
 
 BEGIN
 
@@ -113,13 +105,12 @@ BEGIN
   ------------------------------------------------------------------------------
   u_apertif_unb1_fn_beamformer : ENTITY work.apertif_unb1_fn_beamformer
   GENERIC MAP (
-      g_design_name => "fn_beamformer", --"apertif_unb1_fn_beamformer";
-      g_design_note => "Apertif subband beamformer", --"UNUSED";
+    g_design_name => "apertif_unb1_fn_beamformer_bg_trans",
+    g_design_note => "simulation",
     g_sim         => c_sim,
     g_sim_unb_nr  => c_unb_nr,
     g_sim_node_nr => c_node_nr,
-      g_bf          => c_bf,
-      g_use_bf      => TRUE
+    g_bf          => c_bf
   )
   PORT MAP (
     -- GENERAL
@@ -143,24 +134,24 @@ BEGIN
     ETH_SGOUT   => eth_txp,
     
     -- Transceiver clocks
-      SA_CLK      => sa_clk,  --  : IN  STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+    SA_CLK      => sa_clk,
     SB_CLK      => sb_clk,
 
     -- Mesh Serial I/O
-      FN_BN_0_RX  => fn_bn_0_tx, --          : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-      FN_BN_1_RX  => fn_bn_0_tx, --          : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-      FN_BN_2_RX  => fn_bn_0_tx, --          : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-      FN_BN_3_RX  => fn_bn_0_tx, --          : IN  STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+    FN_BN_0_RX  => fn_bn_0_tx,
+    FN_BN_1_RX  => fn_bn_0_tx,
+    FN_BN_2_RX  => fn_bn_0_tx,
+    FN_BN_3_RX  => fn_bn_0_tx,
 
     -- Serial I/O
-      SI_FN_0_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-      SI_FN_1_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-      SI_FN_2_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-      SI_FN_3_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-      
-      MB_I_in     => phy_in, 
-      MB_I_io     => phy_io, 
-      MB_I_ou     => phy_ou 
+    SI_FN_0_RX  => si_fn_0_tx,
+    SI_FN_1_RX  => si_fn_0_tx,
+    SI_FN_2_RX  => si_fn_0_tx,
+    SI_FN_3_RX  => si_fn_0_tx,
+    
+    MB_I_in     => phy_in_x, 
+    MB_I_io     => OPEN, 
+    MB_I_ou     => OPEN
   );  
 
 END tb;