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Commit 54cd9ed1 authored by Eric Kooistra's avatar Eric Kooistra
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Use tech_pll_lib.tech_pll_xgmii_mac_clocks to create the 312.5 and 156.25 MHz... 

Use tech_pll_lib.tech_pll_xgmii_mac_clocks to create the 312.5 and 156.25 MHz clocks for Arria10 IP.
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libraries/technology/eth_10g/hdllib.cfg
+ 1
− 1
View file @ 54cd9ed1
hdl_lib_name = tech_eth_10g
hdl_library_clause_name = tech_eth_10g_lib
hdl_lib_uses = technology tech_mac_10g tech_10gbase_r common dp
hdl_lib_uses = technology tech_pll tech_mac_10g tech_10gbase_r common dp
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
......
libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+ 43
− 36
View file @ 54cd9ed1
......@@ -28,7 +28,7 @@
-- > as 10
-- > run -all
LIBRARY IEEE, technology_lib, tech_mac_10g_lib, common_lib, dp_lib;
LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -42,7 +42,7 @@ USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
USE tech_mac_10g_lib.tb_tech_mac_10g_pkg.ALL;
USE tech_pll_lib.tech_pll_component_pkg.ALL;
ENTITY tb_tech_eth_10g IS
-- Test bench control parameters
......@@ -58,7 +58,6 @@ END tb_tech_eth_10g;
ARCHITECTURE tb OF tb_tech_eth_10g IS
CONSTANT mm_clk_period : TIME := 20 ns; -- 50 MHz
CONSTANT tx_ref_clk_156_period : TIME := 6.4 ns; -- 156.25 MHz
CONSTANT phy_delay : TIME := 0 ns;
CONSTANT c_st_loopback : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
......@@ -86,12 +85,10 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock
SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
SIGNAL tx_ref_clk_312 : STD_LOGIC := '1'; -- mac_10g
SIGNAL tx_ref_clk_156 : STD_LOGIC := '0'; -- mac_10g reference clock
SIGNAL tx_rst : STD_LOGIC; -- reset synchronous with tx_ref_clk_156
SIGNAL rx_phy_clk_312 : STD_LOGIC := '1'; -- mac_10g
SIGNAL rx_phy_clk_156 : STD_LOGIC := '0'; -- mac_10g rx clock from phy = tx_ref_clk_156 in this tb
SIGNAL rx_rst : STD_LOGIC; -- reset synchronous with rx_phy_clk_156 = tx_ref_clk_156 in this tb
SIGNAL tr_ref_clk_644 : STD_LOGIC := '1'; -- 10base_r reference clock
SIGNAL clk_312 : STD_LOGIC;
SIGNAL clk_156 : STD_LOGIC;
SIGNAL rst_156 : STD_LOGIC;
-- 10G MAC control interface
SIGNAL mm_init : STD_LOGIC := '1';
......@@ -107,18 +104,20 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
SIGNAL tx_siso : t_dp_siso;
SIGNAL tx_siso_arr : t_dp_siso_arr(0 DOWNTO 0);
SIGNAL tx_sosi : t_dp_sosi;
SIGNAL tx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
SIGNAL tx_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
SIGNAL tx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
-- 10G MAC receive interface
-- . The tb is the ST sink
SIGNAL rx_siso : t_dp_siso;
SIGNAL rx_siso_arr : t_dp_siso_arr(0 DOWNTO 0);
SIGNAL rx_sosi : t_dp_sosi;
SIGNAL rx_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
-- 10G PHY serial interface
SIGNAL tx_serial_arr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_serial_arr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL tx_serial_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL rx_serial_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
-- Verification
SIGNAL expected_sosi_arr : t_dp_sosi_arr(0 TO c_nof_pkt-1);
......@@ -130,14 +129,8 @@ BEGIN
-- run 50 us
mm_clk <= NOT mm_clk AFTER mm_clk_period/2; -- MM clock
tx_ref_clk_156 <= NOT tx_ref_clk_156 AFTER tx_ref_clk_156_period/2; -- mac_10g tx reference clock
tx_ref_clk_312 <= NOT tx_ref_clk_312 AFTER tx_ref_clk_156_period/4;
rx_phy_clk_156 <= tx_ref_clk_156; -- use tx_ref_clk_156 to model PHY
rx_phy_clk_312 <= tx_ref_clk_312;
mm_rst <= '1', '0' AFTER mm_clk_period*10;
tx_rst <= '1', '0' AFTER tx_ref_clk_156_period*10;
rx_rst <= '1', '0' AFTER tx_ref_clk_156_period*10;
-- debug signals to ease monitoring in wave window
tx_sosi_data <= tx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0);
......@@ -174,9 +167,9 @@ BEGIN
tx_sosi <= c_dp_sosi_rst;
WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(tx_ref_clk_156);
WAIT UNTIL rising_edge(clk_156);
END LOOP;
proc_common_wait_some_cycles(tx_ref_clk_156, 10);
proc_common_wait_some_cycles(clk_156, 3125); -- 20 us
-- Loopback txp->rxp so use promiscuous mode or use DST_MAC = c_src_mac to send to itself
......@@ -186,12 +179,12 @@ BEGIN
-- . For I>46 the payload length is I and empty = 4 - (I mod 4)
FOR I IN 0 TO c_nof_pkt-1 LOOP
proc_tech_mac_10g_tx_packet(total_header, c_pkt_length_arr(I), g_data_type, c_rl, c_nof_tx_not_valid, tx_ref_clk_156, tx_en, tx_siso, tx_sosi);
proc_common_wait_some_cycles(tx_ref_clk_156, 0);
proc_tech_mac_10g_tx_packet(total_header, c_pkt_length_arr(I), g_data_type, c_rl, c_nof_tx_not_valid, clk_156, tx_en, tx_siso, tx_sosi);
proc_common_wait_some_cycles(clk_156, 0);
END LOOP;
proc_common_wait_some_cycles(tx_ref_clk_156, c_pkt_length_arr(c_nof_pkt-1)/c_tech_mac_10g_symbols_per_beat);
proc_common_wait_some_cycles(tx_ref_clk_156, 100);
proc_common_wait_some_cycles(clk_156, c_pkt_length_arr(c_nof_pkt-1)/c_tech_mac_10g_symbols_per_beat);
proc_common_wait_some_cycles(clk_156, 100);
tb_end <= '1';
WAIT;
END PROCESS;
......@@ -203,22 +196,22 @@ BEGIN
rx_siso <= c_dp_siso_hold;
WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(rx_phy_clk_156);
WAIT UNTIL rising_edge(clk_156);
END LOOP;
-- Receive forever
WHILE TRUE LOOP
proc_tech_mac_10g_rx_packet(total_header, g_data_type, rx_phy_clk_156, rx_sosi, rx_siso);
proc_tech_mac_10g_rx_packet(total_header, g_data_type, clk_156, rx_sosi, rx_siso);
END LOOP;
WAIT;
END PROCESS;
p_ff_store_tx_sosi_at_eop : PROCESS(tx_ref_clk_156)
p_ff_store_tx_sosi_at_eop : PROCESS(clk_156)
VARIABLE vI : NATURAL := 0;
BEGIN
IF rising_edge(tx_ref_clk_156) THEN
IF rising_edge(clk_156) THEN
IF tx_sosi.eop='1' THEN
expected_sosi_arr(vI) <= tx_sosi;
vI := vI +1;
......@@ -226,11 +219,11 @@ BEGIN
END IF;
END PROCESS;
p_ff_verify_rx_sosi_at_eop : PROCESS(rx_phy_clk_156)
p_ff_verify_rx_sosi_at_eop : PROCESS(clk_156)
VARIABLE vI : NATURAL := 0;
VARIABLE vLow : NATURAL := 0;
BEGIN
IF rising_edge(rx_phy_clk_156) THEN
IF rising_edge(clk_156) THEN
IF rx_sosi.eop='1' THEN
-- frame shorter than 64 get padded so em
IF c_pkt_length_arr(vI) < 64 - 14 - 20 - 8 - 4 THEN -- = minimum frame 64 - ETH 14 - IP 20 - UDP 8 - CRC 4
......@@ -258,6 +251,20 @@ BEGIN
rx_siso_arr(0) <= rx_siso;
rx_sosi <= rx_sosi_arr(0);
tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER tech_pll_clk_644_period/2;
pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
GENERIC MAP (
g_technology => g_technology
)
PORT MAP (
refclk_644 => tr_ref_clk_644,
clk_156 => clk_156,
clk_312 => clk_312,
rst_156 => rst_156,
rst_312 => OPEN
);
gen_dut : IF c_st_loopback=FALSE GENERATE
dut : ENTITY work.tech_eth_10g
GENERIC MAP (
......@@ -269,7 +276,7 @@ BEGIN
)
PORT MAP (
-- Transceiver PLL reference clock
tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
tr_ref_clk_644 => tr_ref_clk_644,
-- MM
mm_clk => mm_clk,
......@@ -279,9 +286,9 @@ BEGIN
mac_miso => mm_miso,
-- Clocks
clk_312 => tx_ref_clk_312,
clk_156 => tx_ref_clk_156, -- 156.25 MHz local reference
rst_156 => tx_rst,
clk_312 => clk_312,
clk_156 => clk_156, -- 156.25 MHz local reference
rst_156 => rst_156,
-- ST
tx_snk_in_arr => tx_sosi_arr, -- 64 bit data @ clk_156
......@@ -305,8 +312,8 @@ BEGIN
rx_serial_arr <= TRANSPORT tx_serial_arr AFTER phy_delay;
-- Verification
tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(tx_ref_clk_156);
rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(rx_phy_clk_156);
tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(clk_156);
rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(clk_156);
p_tb_end : PROCESS
BEGIN
......
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