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Commit 54899de5 authored by Reinier van der Walle's avatar Reinier van der Walle
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final changes to testbench

parent 8d7c17ff
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!93resolves L2SDP-191
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applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
+ 2
− 1
View file @ 54899de5
hdl_lib_name = lofar2_unb2b_ring_bsp
hdl_library_clause_name = lofar2_unb2b_ring_bsp_lib
hdl_lib_uses_synth = common technology tech_pll dp unb2b_board diag ta2_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io lofar2_sdp
hdl_lib_uses_synth = common technology tech_pll dp mm unb2b_board diag ta2_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io lofar2_sdp
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
hdl_lib_include_ip =
......@@ -15,6 +15,7 @@ synth_files =
top.vhd
test_bench_files =
tb_lofar2_unb2b_ring_bsp.vhd
regression_test_vhdl =
......
applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
+ 2
− 3
View file @ 54899de5
......@@ -153,7 +153,6 @@ BEGIN
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
------------------------------------------------------------------------------
......@@ -165,7 +164,7 @@ BEGIN
g_design_note => "",
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr,
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
......@@ -296,7 +295,7 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 3 , tb_clk);
proc_common_wait_some_cycles(ext_clk, 5* c_nof_block_per_sync * 1000);
proc_common_wait_some_cycles(ext_clk, 2* c_nof_block_per_sync * 1000);
---------------------------------------------------------------------------
-- Read TX monitor
......
applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+ 18
− 11
View file @ 54899de5
......@@ -30,12 +30,14 @@
-- . M&C
-- --------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, tech_pll_lib, dp_lib, diag_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib, lofar2_sdp_lib;
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, tech_pll_lib, dp_lib, diag_lib, mm_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib, lofar2_sdp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
......@@ -109,6 +111,8 @@ ARCHITECTURE str OF top IS
---------------
-- Constants
---------------
CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
-- QSFP
CONSTANT c_nof_qsfp_bus : NATURAL := 1;
CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus; --4
......@@ -687,7 +691,8 @@ BEGIN
-----------------------------------------------------------------------------
u_dp_demux_rx_monitor : ENTITY dp_lib.dp_demux
GENERIC MAP(
g_nof_output => g_nof_rx_monitors
g_nof_output => g_nof_rx_monitors,
g_sel_ctrl_invert => TRUE
)
PORT MAP(
rst => st_rst,
......@@ -725,7 +730,8 @@ BEGIN
-----------------------------------------------------------------------------
u_dp_demux_tx_monitor : ENTITY dp_lib.dp_demux
GENERIC MAP(
g_nof_output => g_nof_tx_monitors
g_nof_output => g_nof_tx_monitors,
g_sel_ctrl_invert => TRUE
)
PORT MAP(
rst => st_rst,
......@@ -932,7 +938,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Freeze wrapper instantiation
-----------------------------------------------------------------------------
gen_opencl: IF g_sim = FLASE GENERATE
gen_opencl: IF g_sim = FALSE GENERATE
freeze_wrapper_inst : freeze_wrapper
PORT MAP(
board_kernel_clk_clk => board_kernel_clk_clk,
......@@ -1172,20 +1178,21 @@ BEGIN
gen_sim: IF g_sim = TRUE GENERATE
i_kernel_rst <= NOT i_reset_n;
board_kernel_clk_clk <= st_clk;
u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
u_mm_file_reg_dp_xonoff_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
u_mm_file_reg_dp_xonoff_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
u_mm_file_reg_dp_xonoff_from_lane: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
u_mm_file_reg_dp_xonoff_from_lane: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
u_mm_file_reg_bsn_monitor_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
u_mm_file_reg_bsn_monitor_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
u_mm_file_reg_bsn_monitor_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
u_mm_file_reg_bsn_monitor_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
u_mm_file_reg_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
u_mm_file_reg_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
PORT MAP(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
END GENERATE
END GENERATE;
i_reset_n <= NOT mm_rst; -- First reset OpenCL components in qsys (board)
-- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
......
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