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Commit 5476475b authored by Eric Kooistra's avatar Eric Kooistra
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Use rd_reg. Now also verify g_mm_broadcast=FALSE AND g_nof_streams>1

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libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+ 82
− 32
View file @ 5476475b
......@@ -37,6 +37,7 @@ USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
USE work.diag_pkg.ALL;
USE work.tb_diag_pkg.ALL;
ENTITY tb_mms_diag_seq IS
......@@ -44,8 +45,8 @@ ENTITY tb_mms_diag_seq IS
-- general
g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
-- specific
g_nof_streams : NATURAL := 2;
g_mm_broadcast_tx : BOOLEAN := TRUE;
g_nof_streams : NATURAL := 1;
g_mm_broadcast_tx : BOOLEAN := FALSE;
g_data_w : NATURAL := 40; -- >= g_seq_dat_w
g_seq_dat_w : NATURAL := 32
);
......@@ -55,12 +56,14 @@ ARCHITECTURE str of tb_mms_diag_seq IS
CONSTANT mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_random_w : NATURAL := 16;
SIGNAL random : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL random : STD_LOGIC_VECTOR(c_random_w-1 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL ready : STD_LOGIC;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL tb_mode : t_tb_diag_seq_mode_enum := s_off;
SIGNAL tb_mode_multi : t_tb_diag_seq_mode_enum := s_off;
SIGNAL tb_verify : STD_LOGIC := '0';
SIGNAL mm_rst : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC := '0';
......@@ -73,11 +76,12 @@ ARCHITECTURE str of tb_mms_diag_seq IS
SIGNAL reg_rx_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_rx_miso : t_mem_miso;
SIGNAL rd_reg : t_diag_seq_mm_reg;
SIGNAL rd_reg_arr : t_diag_seq_mm_reg_arr(g_nof_streams DOWNTO 0); -- use +1 to support g_nof_streams=1, 2 in p_stimuli_and_verify
SIGNAL tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL tx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL stream_index : NATURAL;
SIGNAL force_low_error : STD_LOGIC;
SIGNAL force_replicate_error : STD_LOGIC;
......@@ -107,104 +111,148 @@ BEGIN
-- Stimuli
------------------------------------------------------------------------------
p_stimuli_and_verify : PROCESS
-- Cannot use non static rd_reg_arr(I) variable index in procedure argument, therefor use constant index rd_reg_arr(c_st_0) or rd_reg_arr(c_st_1).
CONSTANT c_st_0 : NATURAL := 0;
CONSTANT c_st_1 : NATURAL := 1;
BEGIN
stream_index <= 0; -- default verify stream 0
force_low_error <= '0';
force_replicate_error <= '0';
tb_mode <= s_off;
proc_common_wait_until_low(mm_clk, mm_rst);
proc_common_wait_some_cycles(mm_clk, 10);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
-------------------------------------------------------------------------
-- Verify s_off
-------------------------------------------------------------------------
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
IF g_nof_streams>1 THEN
stream_index <= 1; -- try stream 1
proc_diag_seq_verify(c_st_1, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode_multi, tb_verify, rd_reg_arr(c_st_1));
stream_index <= 0; -- back to stream 0
END IF;
-------------------------------------------------------------------------
-- Verify Tx and Rx on and both with the same pattern
-------------------------------------------------------------------------
tb_mode <= s_expect_ok;
proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_enable("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_rx_enable("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_rx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_tx_enable(c_st_0, "CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_rx_enable(c_st_0, "CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
-- Run test and read and verify Rx status
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
-- Check that there is valid data
IF g_flow_control_verify=e_active THEN
ASSERT rx_snk_in_arr(0).valid='1' REPORT "Wrong diag result: no valid data at rx_snk_in_arr(0)." SEVERITY ERROR;
END IF;
-------------------------------------------------------------------------
-- Verify Tx and Rx on but with different pattern
-------------------------------------------------------------------------
tb_mode <= s_expect_error;
proc_diag_seq_tx_enable("PSRG", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_enable(c_st_0, "PSRG", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
-- Run test and read and verify Rx status
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
-------------------------------------------------------------------------
-- Verify Rx off
-------------------------------------------------------------------------
tb_mode <= s_expect_no_result;
proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_rx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
-- Run test and read and verify Rx status
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
IF g_mm_broadcast_tx=FALSE THEN
-------------------------------------------------------------------------
-- Verify Tx and Rx on with error in sequence low part
-------------------------------------------------------------------------
tb_mode <= s_expect_ok;
proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_enable("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_rx_enable("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_rx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_tx_enable(c_st_0, "CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_rx_enable(c_st_0, "CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
-- Run test and read and verify Rx status
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
tb_mode <= s_expect_error;
proc_common_wait_some_cycles(dp_clk, 1);
force_low_error <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
proc_common_wait_some_cycles(dp_clk, c_random_w); -- sufficently long to affect a valid data in case g_flow_control_verify=e_random
force_low_error <= '0';
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
END IF;
IF g_mm_broadcast_tx=FALSE AND g_data_w>g_seq_dat_w THEN
-------------------------------------------------------------------------
-- Verify Tx and Rx on with error in sequence replicate part
-------------------------------------------------------------------------
tb_mode <= s_expect_ok;
proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_rx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_enable("CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_rx_enable("CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_rx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_tx_enable(c_st_0, "CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_rx_enable(c_st_0, "CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
-- Run test and read and verify Rx status
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
tb_mode <= s_expect_error;
proc_common_wait_some_cycles(dp_clk, 1);
force_replicate_error <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
proc_common_wait_some_cycles(dp_clk, c_random_w); -- sufficently long to affect a valid data in case g_flow_control_verify=e_random
force_replicate_error <= '0';
proc_common_wait_some_cycles(mm_clk, 200);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
END IF;
IF g_mm_broadcast_tx=FALSE AND g_nof_streams>1 THEN
stream_index <= 1; -- try stream 1
-------------------------------------------------------------------------
-- Verify Tx and Rx on and both with the same pattern for stream 1
-------------------------------------------------------------------------
proc_diag_seq_tx_disable(c_st_1, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_1));
proc_diag_seq_rx_disable(c_st_1, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_1));
proc_diag_seq_tx_enable(c_st_1, "CNTR", 17, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_1));
proc_diag_seq_rx_enable(c_st_1, "CNTR", mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_1));
-- Run test and read and verify Rx status
proc_common_wait_some_cycles(mm_clk, 200);
tb_mode_multi <= s_expect_ok;
proc_diag_seq_verify(c_st_1, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode_multi, tb_verify, rd_reg_arr(c_st_1));
-- Check that there is valid data
IF g_flow_control_verify=e_active THEN
ASSERT rx_snk_in_arr(1).valid='1' REPORT "Wrong diag result: no valid data at rx_snk_in_arr(1)." SEVERITY ERROR;
END IF;
stream_index <= 0; -- back to stream 0
END IF;
-------------------------------------------------------------------------
-- Both off
-------------------------------------------------------------------------
tb_mode <= s_off;
proc_diag_seq_tx_disable(mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg);
proc_diag_seq_tx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_diag_seq_rx_disable(c_st_0, mm_clk, dp_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, rd_reg_arr(c_st_0));
proc_common_wait_some_cycles(mm_clk, 100);
proc_diag_seq_verify(mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg);
proc_diag_seq_verify(c_st_0, mm_clk, reg_tx_miso, reg_tx_mosi, reg_rx_miso, reg_rx_mosi, tb_mode, tb_verify, rd_reg_arr(c_st_0));
proc_common_wait_some_cycles(mm_clk, 10);
tb_end <= '1';
WAIT;
END PROCESS;
p_verify_mm_broadcast : PROCESS(rx_snk_in_arr)
VARIABLE v_snk_in : t_dp_sosi;
BEGIN
......@@ -265,7 +313,9 @@ BEGIN
p_connect : PROCESS(tx_src_out_arr, force_low_error, force_replicate_error)
BEGIN
-- Default lopoback all streams
rx_snk_in_arr <= tx_src_out_arr;
-- Optionally apply errors on stream 0
IF force_low_error='1' THEN
rx_snk_in_arr(0).data(0) <= NOT tx_src_out_arr(0).data(0);
END IF;
......
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