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Commit 53eeddd4 authored by Zanting's avatar Zanting
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Aligned interfaces

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libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+ 94
− 90
View file @ 53eeddd4
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
// GENERATION: XML // GENERATION: XML
// ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v // ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
// Generated using ACDS version 11.1sp2 259 at 2015.08.17.16:33:44 // Generated using ACDS version 11.1sp2 259 at 2015.10.12.13:35:00
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
module ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ( module ip_stratixiv_ddr3_uphy_16g_dual_rank_800 (
...@@ -42,6 +42,8 @@ module ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ( ...@@ -42,6 +42,8 @@ module ip_stratixiv_ddr3_uphy_16g_dual_rank_800 (
output wire local_cal_fail, // .local_cal_fail output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup input wire oct_rup, // .rup
output wire [13:0] seriesterminationcontrol, // oct_sharing.seriesterminationcontrol
output wire [13:0] parallelterminationcontrol, // .parallelterminationcontrol
output wire pll_mem_clk, // pll_sharing.pll_mem_clk output wire pll_mem_clk, // pll_sharing.pll_mem_clk
output wire pll_write_clk, // .pll_write_clk output wire pll_write_clk, // .pll_write_clk
output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
...@@ -89,6 +91,8 @@ module ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ( ...@@ -89,6 +91,8 @@ module ip_stratixiv_ddr3_uphy_16g_dual_rank_800 (
.local_cal_fail (local_cal_fail), // .local_cal_fail .local_cal_fail (local_cal_fail), // .local_cal_fail
.oct_rdn (oct_rdn), // oct.rdn .oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup .oct_rup (oct_rup), // .rup
.seriesterminationcontrol (seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (parallelterminationcontrol), // .parallelterminationcontrol
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk .pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_write_clk), // .pll_write_clk .pll_write_clk (pll_write_clk), // .pll_write_clk
.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk .pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
...@@ -319,7 +323,7 @@ endmodule ...@@ -319,7 +323,7 @@ endmodule
// Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" /> // Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
// Retrieval info: <generic name="PLL_SHARING_MODE" value="Master" /> // Retrieval info: <generic name="PLL_SHARING_MODE" value="Master" />
// Retrieval info: <generic name="DLL_SHARING_MODE" value="Master" /> // Retrieval info: <generic name="DLL_SHARING_MODE" value="Master" />
// Retrieval info: <generic name="OCT_SHARING_MODE" value="None" /> // Retrieval info: <generic name="OCT_SHARING_MODE" value="Master" />
// Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" /> // Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
// Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" /> // Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
// Retrieval info: <generic name="USE_FAKE_PHY" value="false" /> // Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
......
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