Recreated the hw_tcl file for avs2 in RADIOHDL using the Component Editor GUI.

libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl

-# TCL File Generated by Component Editor 10.0
-# Wed Apr 20 13:44:54 CEST 2011
+# TCL File Generated by Component Editor 11.1sp2
+# Wed Jul 23 09:36:00 CEST 2014
 # DO NOT MODIFY
 
 
 # +-----------------------------------
 # | 
 # | avs2_eth_coe "avs2_eth_coe" v1.0
-# | ASTRON 2011.04.20.13:44:54
+# | ASTRON 2014.07.23.09:36:00
 # | MM slave port to conduit for the ETH module
 # | 
-# | D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/tse/src/vhdl/avs2_eth_coe.vhd
+# | /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
 # | 
 # |    ./avs2_eth_coe.vhd syn, sim
-# |    ./D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd syn, sim
-# |    ./D:/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# |    ./tse_pkg.vhd syn, sim
-# |    ./eth_layers_pkg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
 # |    ./eth_pkg.vhd syn, sim
+# |    /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
 # | 
 # +-----------------------------------
 
 # +-----------------------------------
-# | request TCL package from ACDS 10.0
+# | request TCL package from ACDS 11.0
 # | 
-package require -exact sopc 10.0
+package require -exact sopc 11.0
 # | 
 # +-----------------------------------
 
@@ -34,6 +34,7 @@ set_module_property DESCRIPTION "MM slave port to conduit for the ETH module"
 set_module_property NAME avs2_eth_coe
 set_module_property VERSION 1.0
 set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property GROUP Uniboard
 set_module_property AUTHOR ASTRON
 set_module_property DISPLAY_NAME avs2_eth_coe
@@ -42,6 +43,8 @@ set_module_property TOP_LEVEL_HDL_MODULE avs2_eth_coe
 set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
 set_module_property EDITABLE true
 set_module_property ANALYZE_HDL TRUE
+set_module_property STATIC_TOP_LEVEL_MODULE_NAME ""
+set_module_property FIX_110_VIP_PATH false
 # | 
 # +-----------------------------------
 
@@ -49,11 +52,11 @@ set_module_property ANALYZE_HDL TRUE
 # | files
 # | 
 add_file avs2_eth_coe.vhd {SYNTHESIS SIMULATION}
-add_file ../../../common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
-add_file ../../../dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
-add_file tse_pkg.vhd {SYNTHESIS SIMULATION}
-add_file eth_layers_pkg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/common_pkg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/dp/src/vhdl/dp_stream_pkg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/technology/tse/tech_tse_pkg.vhd {SYNTHESIS SIMULATION}
 add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
+add_file /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd {SYNTHESIS SIMULATION}
 # | 
 # +-----------------------------------
 
@@ -73,20 +76,35 @@ add_file eth_pkg.vhd {SYNTHESIS SIMULATION}
 # | connection point mm
 # | 
 add_interface mm clock end
+set_interface_property mm clockRate 0
 
 set_interface_property mm ENABLED true
 
-add_interface_port mm csi_mm_reset reset Input 1
 add_interface_port mm csi_mm_clk clk Input 1
 # | 
 # +-----------------------------------
 
+# +-----------------------------------
+# | connection point mm_reset
+# | 
+add_interface mm_reset reset end
+set_interface_property mm_reset associatedClock mm
+set_interface_property mm_reset synchronousEdges DEASSERT
+
+set_interface_property mm_reset ENABLED true
+
+add_interface_port mm_reset csi_mm_reset reset Input 1
+# | 
+# +-----------------------------------
+
 # +-----------------------------------
 # | connection point mms_tse
 # | 
 add_interface mms_tse avalon end
 set_interface_property mms_tse addressAlignment DYNAMIC
+set_interface_property mms_tse addressUnits WORDS
 set_interface_property mms_tse associatedClock mm
+set_interface_property mms_tse associatedReset mm_reset
 set_interface_property mms_tse burstOnBurstBoundariesOnly false
 set_interface_property mms_tse explicitAddressSpan 0
 set_interface_property mms_tse holdTime 0
@@ -101,7 +119,6 @@ set_interface_property mms_tse setupTime 0
 set_interface_property mms_tse timingUnits Cycles
 set_interface_property mms_tse writeWaitTime 0
 
-set_interface_property mms_tse ASSOCIATED_CLOCK mm
 set_interface_property mms_tse ENABLED true
 
 add_interface_port mms_tse mms_tse_address address Input 10
@@ -118,7 +135,9 @@ add_interface_port mms_tse mms_tse_waitrequest waitrequest Output 1
 # | 
 add_interface mms_reg avalon end
 set_interface_property mms_reg addressAlignment DYNAMIC
+set_interface_property mms_reg addressUnits WORDS
 set_interface_property mms_reg associatedClock mm
+set_interface_property mms_reg associatedReset mm_reset
 set_interface_property mms_reg burstOnBurstBoundariesOnly false
 set_interface_property mms_reg explicitAddressSpan 0
 set_interface_property mms_reg holdTime 0
@@ -134,7 +153,6 @@ set_interface_property mms_reg setupTime 0
 set_interface_property mms_reg timingUnits Cycles
 set_interface_property mms_reg writeWaitTime 0
 
-set_interface_property mms_reg ASSOCIATED_CLOCK mm
 set_interface_property mms_reg ENABLED true
 
 add_interface_port mms_reg mms_reg_address address Input 4
@@ -150,7 +168,9 @@ add_interface_port mms_reg mms_reg_readdata readdata Output 32
 # | 
 add_interface mms_ram avalon end
 set_interface_property mms_ram addressAlignment DYNAMIC
+set_interface_property mms_ram addressUnits WORDS
 set_interface_property mms_ram associatedClock mm
+set_interface_property mms_ram associatedReset mm_reset
 set_interface_property mms_ram burstOnBurstBoundariesOnly false
 set_interface_property mms_ram explicitAddressSpan 0
 set_interface_property mms_ram holdTime 0
@@ -166,7 +186,6 @@ set_interface_property mms_ram setupTime 0
 set_interface_property mms_ram timingUnits Cycles
 set_interface_property mms_ram writeWaitTime 0
 
-set_interface_property mms_ram ASSOCIATED_CLOCK mm
 set_interface_property mms_ram ENABLED true
 
 add_interface_port mms_ram mms_ram_address address Input 10
@@ -183,8 +202,8 @@ add_interface_port mms_ram mms_ram_readdata readdata Output 32
 add_interface interrupt interrupt end
 set_interface_property interrupt associatedAddressablePoint mms_reg
 set_interface_property interrupt associatedClock mm
+set_interface_property interrupt associatedReset mm_reset
 
-set_interface_property interrupt ASSOCIATED_CLOCK mm
 set_interface_property interrupt ENABLED true
 
 add_interface_port interrupt ins_interrupt_irq irq Output 1