Added g_big_endian_wb_in and g_big_endian_wb_out, and added p_verify_data_scope.

libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd

@@ -89,6 +89,8 @@ use work.fil_pkg.all;
 entity tb_fil_ppf_wide_file_data is
   generic(
     -- generics for tb
+    g_big_endian_wb_in  : boolean := true;
+    g_big_endian_wb_out : boolean := true;
     g_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
       -- type t_fil_pipeline is record
       --   -- generic for the taps and coefficients memory
@@ -211,7 +213,7 @@ begin
   --   in_dat_arr [wb_factor][nof_streams] [t][nof_channels]  int
   -- 
   -- The time to wb_factor mapping for the fil_ppf_wide is big endian,
-  -- so [3:0] = [t0,t1,t2,t3]
+  -- so [3:0] = [t0,t1,t2,t3], when g_big_endian_wb_in = TRUE.
   -- When wb_factor = 4 and nof_streams = 2 then the mapping is as
   -- follows (S = stream index, P = wideband factor index):
   --
@@ -240,7 +242,11 @@ begin
     for I in 0 to g_data_file_nof_read/g_fil_ppf.wb_factor-1 loop  -- serial
       for K in 0 to c_nof_channels-1 loop  -- serial
         for P in 0 to g_fil_ppf.wb_factor-1 loop  -- parallel
-          vP := g_fil_ppf.wb_factor-1-P;          -- time to big endian
+          if g_big_endian_wb_in=TRUE then
+            vP := g_fil_ppf.wb_factor-1-P;        -- time to wideband big endian
+          else
+            vP := P;                              -- time to wideband little endian
+          end if;
           for S in 0 to g_fil_ppf.nof_streams-1 loop  -- parallel
             if S=1 then
               -- if present then stream 1 carries zero data to be able to recognize the stream order in the wave window
@@ -275,6 +281,8 @@ begin
   ---------------------------------------------------------------
   u_dut : entity work.fil_ppf_wide
   generic map (
+    g_big_endian_wb_in  => g_big_endian_wb_in,
+    g_big_endian_wb_out => g_big_endian_wb_out,
     g_fil_ppf           => g_fil_ppf,
     g_fil_ppf_pipeline  => g_fil_ppf_pipeline,
     g_coefs_file_prefix => c_coefs_mif_file_prefix
@@ -349,7 +357,11 @@ begin
     if rising_edge(clk) then
       if out_val='1' then
         for P in 0 to g_fil_ppf.wb_factor-1 loop  -- parallel
-          vP := g_fil_ppf.wb_factor-1-P;
+          if g_big_endian_wb_out=true then
+            vP := g_fil_ppf.wb_factor-1-P;        -- time to wideband big endian
+          else
+            vP := P;                              -- time to wideband little endian
+          end if;
           for S in 0 to g_fil_ppf.nof_streams-1 loop  -- parallel
             v_out_dat := TO_SINT(out_dat_arr(vP*g_fil_ppf.nof_streams + S));
             if S=1 then
@@ -397,7 +409,11 @@ begin
     variable vP : natural;
   begin
     for P in 0 to g_fil_ppf.wb_factor-1 loop
+      if g_big_endian_wb_out=true then
         vP := g_fil_ppf.wb_factor-1-P;
+      else
+        vP := P;
+      end if;
       exp_data((vP+1)*c_out_dat_w-1 DOWNTO vP*c_out_dat_w) <= TO_SVEC(expected_data_arr(out_sub_val_cnt*g_fil_ppf.wb_factor + P), c_out_dat_w);
     end loop;
   end process;
@@ -406,7 +422,7 @@ begin
   generic map (
     g_sim                 => TRUE,
     g_wideband_factor     => g_fil_ppf.wb_factor,  -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
-    g_wideband_big_endian => TRUE,                 -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+    g_wideband_big_endian => g_big_endian_wb_in,   -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
     g_dat_w               => c_in_dat_w            -- Actual width of the data samples
   )
   port map (
@@ -426,7 +442,7 @@ begin
   generic map (
     g_sim                 => TRUE,
     g_wideband_factor     => g_fil_ppf.wb_factor,  -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
-    g_wideband_big_endian => TRUE,                 -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+    g_wideband_big_endian => g_big_endian_wb_out,  -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
     g_dat_w               => c_out_dat_w            -- Actual width of the data samples
   )
   port map (
@@ -446,7 +462,7 @@ begin
   generic map (
     g_sim                 => TRUE,
     g_wideband_factor     => g_fil_ppf.wb_factor,  -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
-    g_wideband_big_endian => TRUE,                 -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
+    g_wideband_big_endian => g_big_endian_wb_out,  -- When true in_data[3:0] = sample[t0,t1,t2,t3], else when false : in_data[3:0] = sample[t3,t2,t1,t0]
     g_dat_w               => c_out_dat_w            -- Actual width of the data samples
   )
   port map (
@@ -464,4 +480,13 @@ begin
 
   diff_data_scope <= exp_data_scope - output_data_scope;
 
+  -- Equivalent to p_verify_output, but using the sclk scope data
+  p_verify_data_scope : process(sclk)
+  begin
+    if rising_edge(clk) then
+      assert diff_data_scope <=  c_diff_margin and
+             diff_data_scope >= -c_diff_margin report "Output data scope error" severity error;
+    end if;
+  end process;
+
 end tb;
\ No newline at end of file

libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd

@@ -48,6 +48,8 @@ ARCHITECTURE tb OF tb_tb_fil_ppf_wide_file_data IS
   
 BEGIN
 
+--g_big_endian_wb_in  : boolean := true;
+--g_big_endian_wb_out : boolean := true;
 --g_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
 --  -- type t_fil_pipeline is record
 --  --   -- generic for the taps and coefficients memory
@@ -82,15 +84,17 @@ BEGIN
 --g_enable_in_val_gaps  : boolean := FALSE
 
   -- verify fil_ppf_wide for wb_factor=1, so effectively same as using fil_ppf_single directly
-  u1_act                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (1, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600, 25600, FALSE);
-  u1_act_15taps           : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (1, 0, 128, 15, 1, 1, 8, 16, 16), c_coeff_prefix, c_data15, 25600,  5000, FALSE);
-  u1_rnd                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (1, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
-  u1_rnd_channels_streams : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (1, 1, 128, 16, 2, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
+  u1_act                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (TRUE, TRUE, c_pipeline, (1, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600, 25600, FALSE);
+  u1_act_15taps           : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (TRUE, TRUE, c_pipeline, (1, 0, 128, 15, 1, 1, 8, 16, 16), c_coeff_prefix, c_data15, 25600,  5000, FALSE);
+  u1_rnd                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (TRUE, TRUE, c_pipeline, (1, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
+  u1_rnd_channels_streams : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (TRUE, TRUE, c_pipeline, (1, 1, 128, 16, 2, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
   
-  -- verify fil_ppf_wide for wb_factor>1
-  u4_act                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (4, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600, 25600, FALSE);
-  u4_act_15taps           : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (4, 0, 128, 15, 1, 1, 8, 16, 16), c_coeff_prefix, c_data15, 25600,  5000, FALSE);
-  u4_rnd                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (4, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
-  u4_rnd_channels_streams : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (c_pipeline, (4, 1, 128, 16, 4, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
+  -- verify fil_ppf_wide for wb_factor>1 (be = big endian, le = little endian)
+  u4_act                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP ( TRUE,  TRUE, c_pipeline, (4, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600, 25600, FALSE);
+  u4_act_be_le            : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP ( TRUE, FALSE, c_pipeline, (4, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600, 25600, FALSE);
+  u4_act_le_le            : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP (FALSE, FALSE, c_pipeline, (4, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600, 25600, FALSE);
+  u4_act_15taps           : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP ( TRUE,  TRUE, c_pipeline, (4, 0, 128, 15, 1, 1, 8, 16, 16), c_coeff_prefix, c_data15, 25600,  5000, FALSE);
+  u4_rnd                  : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP ( TRUE,  TRUE, c_pipeline, (4, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
+  u4_rnd_channels_streams : ENTITY work.tb_fil_ppf_wide_file_data GENERIC MAP ( TRUE,  TRUE, c_pipeline, (4, 1, 128, 16, 4, 1, 8, 16, 16), c_coeff_prefix, c_data,   25600,  5000, TRUE);
 
 END tb;