Fix simulating DDR4 for unb2c, except for fverifying the dbg_rd_data.

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -29,7 +29,6 @@
 -- > as 10
 -- > run -all 
 --
-
 LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, diagnostics_lib;                   
 USE IEEE.STD_LOGIC_1164.ALL;    
 USE IEEE.numeric_std.ALL;
@@ -164,6 +163,7 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL dbg_c_ctlr_wr_not_rd_arr     : STD_LOGIC_VECTOR(0 TO c_nof_access-1)  := c_ctlr_wr_not_rd_arr;
   
   SIGNAL dbg_c_tech_ddr               : t_c_tech_ddr := c_tech_ddr;
+  SIGNAL dbg_c_gigabytes              : NATURAL := c_gigabytes;  -- = 0 for sim model, else nof GB
   SIGNAL dbg_c_dp_data_w              : NATURAL := c_dp_data_w;
   SIGNAL dbg_c_wr_fifo_depth          : NATURAL := c_wr_fifo_depth;
   SIGNAL dbg_c_rd_fifo_depth          : NATURAL := c_rd_fifo_depth;
@@ -309,15 +309,18 @@ BEGIN
       
       -- Check diagnostics sink after the rd fifo has been read empty
       proc_common_wait_some_cycles(dp_clk, 1);
-      ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!"  SEVERITY FAILURE;
+      ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!" SEVERITY FAILURE;
+      --ASSERT snk_diag_res = '0' REPORT "[ERROR] WRONG DIAG_RES!" SEVERITY FAILURE;
+      --FIXME: Add 4GB DDR4 IO driver IP for unb2c and then uncomment ASSERT snk_diag_res and delete this IF-THEN-ELSE.
       IF c_tech_ddr.name = "DDR4" AND g_technology = c_tech_arria10_e2sg THEN
         -- Cannot yet verify DDR4 for g_technology = c_tech_arria10_e2sg (is
         -- unb2c), because we have 8GB DDR4 IO Driver and 4GB DDR4 memory. In
         -- simulation these can connect, but appear to yield dbg_rd_data = 0
         -- causing wrong snk_diag_res.
-        -- FIXME: Add 4GB DDR4 IO driver IP for unb2c.
+        REPORT "Did NOT check snk_diag_res." SEVERITY NOTE;
       ELSE
         ASSERT snk_diag_res = '0' REPORT "[ERROR] WRONG DIAG_RES!" SEVERITY FAILURE;
+        REPORT "Checked snk_diag_res." SEVERITY NOTE;
       END IF;
           
       -- Stop diagnostics sink
@@ -329,7 +332,7 @@ BEGIN
       snk_diag_en <= '1';
     END LOOP;
     
-    -- If the test failed then it would have stopped already, so it the test has passed
+    -- If the test failed then it would have stopped already (due to SEVERITY FAILURE), so if it gets here then the test has passed
     REPORT "[OK] Test passed." SEVERITY NOTE;
 
     -- Stop the simulation

libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd

@@ -24,6 +24,8 @@
 -- Usage:
 --   > as 5
 --   > run -all
+-- # Takes about   10m for DDR3
+-- # Takes about 1u10m for DDR4
 
 LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -41,9 +43,10 @@ ARCHITECTURE tb OF tb_tb_io_ddr IS
 
   CONSTANT c_technology     : NATURAL      := c_tech_select_default;
   CONSTANT c_tech_ddr3      : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-  CONSTANT c_tech_ddr4      : t_c_tech_ddr := c_tech_ddr4_8g_1600m;
+  --CONSTANT c_tech_ddr4      : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
+  CONSTANT c_tech_ddr4      : t_c_tech_ddr := func_tech_sel_ddr(c_technology = c_tech_arria10_e1sg, c_tech_ddr4_4g_1600m, c_tech_ddr4_8g_1600m);  -- use 4GB for unb2b, 8GB for unb2c
   CONSTANT c_tech_ddr       : t_c_tech_ddr := func_tech_sel_ddr(c_technology, c_tech_ddr3, c_tech_ddr4);  -- Select DDR3 or DDR4 dependent on the technology
-  
+
   CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'1');                                             
   SIGNAL   tb_end_vec   : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_tb_end_vec;  -- sufficiently long to fit all tb instances
   SIGNAL   tb_end       : STD_LOGIC := '0';