initial commit of st_xsq_arr.vhd

libraries/dsp/st/hdllib.cfg

@@ -10,6 +10,7 @@ synth_files =
     src/vhdl/st_calc.vhd 
     src/vhdl/st_sst.vhd 
     src/vhdl/st_xsq.vhd 
+    src/vhdl/st_xsq_arr.vhd 
 #    src/vhdl/st_top.vhd 
     src/vhdl/st_histogram.vhd
     src/vhdl/st_histogram_reg.vhd

libraries/dsp/st/src/vhdl/st_xsq_arr.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author : R. vd Walle
+-- Purpose:
+-- Multiple instances of st_xsq.vhd
+-- Description:                                                          
+--   . See st_xsq.vhd
+-- Remarks:
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+ENTITY st_xsq_arr IS
+  GENERIC (
+    g_technology        : NATURAL := c_tech_select_default;
+    g_nof_streams       : NATURAL := 1;
+    g_nof_signal_inputs : NATURAL := 2;
+    g_nof_crosslets     : NATURAL := 1;
+    g_in_data_w         : NATURAL := 18;    -- width of the data to be accumulated
+    g_stat_data_w       : NATURAL := 54;    -- statistics accumulator width
+    g_stat_data_sz      : NATURAL := 2      -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+  );                
+  PORT (            
+    mm_rst : IN  STD_LOGIC;
+    mm_clk : IN  STD_LOGIC;
+    dp_rst : IN  STD_LOGIC;
+    dp_clk : IN  STD_LOGIC;
+                    
+    -- Streaming    
+    in_a_arr : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);   -- Complex input data
+    in_b_arr : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);   -- Complex input data
+    
+    -- Memory Mapped
+    ram_st_xsq_mosi : IN  t_mem_mosi;  
+    ram_st_xsq_miso : OUT t_mem_miso
+  );
+END st_xsq_arr;
+
+ARCHITECTURE str OF st_xsq_arr IS
+
+  CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
+  CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
+  
+  CONSTANT c_nof_stat_w   : NATURAL := ceil_log2(c_nof_statistics);
+  CONSTANT c_nof_word     : NATURAL := g_stat_data_sz*c_nof_statistics*c_nof_complex;
+  CONSTANT c_nof_word_w   : NATURAL := ceil_log2(c_nof_word);
+  CONSTANT c_stat_word_w  : NATURAL := g_stat_data_sz*c_word_w;
+  
+  SIGNAL ram_st_xsq_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+  SIGNAL ram_st_xsq_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+    
+BEGIN
+  -- st_xsq instances
+  gen_xsq : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    st_xsq : ENTITY work.st_xsq 
+    GENERIC MAP (
+      g_technology        => g_technology,
+      g_nof_signal_inputs => g_nof_signal_inputs,
+      g_nof_crosslets     => g_nof_crosslets,
+      g_in_data_w         => g_in_data_w,   
+      g_stat_data_w       => g_stat_data_w,      
+      g_stat_data_sz      => g_stat_data_sz     
+    )
+    PORT MAP (
+  
+      mm_rst => mm_rst, 
+      mm_clk => mm_clk, 
+      dp_rst => dp_rst, 
+      dp_clk => dp_clk, 
+               
+      -- Streaming    
+      in_a => in_a_arr(I),  
+      in_b => in_b_arr(I),  
+      
+      -- Memory Mapped
+      ram_st_xsq_mosi => ram_st_xsq_mosi_arr(I), 
+      ram_st_xsq_miso => ram_st_xsq_miso_arr(I) 
+    );
+  END GENERATE;
+  
+  ---------------------------------------------------------------
+  -- COMBINE MEMORY MAPPED INTERFACES
+  ---------------------------------------------------------------
+  -- Combine the internal array of mm interfaces.
+  u_mem_mux_select : entity common_lib.common_mem_mux
+  generic map (    
+    g_nof_mosi    => g_nof_streams,
+    g_mult_addr_w => c_nof_word_w
+  )
+  port map (
+    mosi     => ram_st_xsq_mosi,
+    miso     => ram_st_xsq_miso,
+    mosi_arr => ram_st_xsq_mosi_arr,
+    miso_arr => ram_st_xsq_miso_arr
+  );
+ 
+  
+END str;