Updated sensitivity list in several processes.

libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd

@@ -169,7 +169,7 @@ BEGIN
         sample_store_irq_irq       => open
     );
 
-    PROCESS(eoc, mm_rst)
+    PROCESS(mm_clk, mm_rst)
       BEGIN
         IF mm_rst = '1' THEN
           controller_csr_write <= '0';

libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd

@@ -95,7 +95,7 @@ ARCHITECTURE rtl of nw_ping_response IS
 BEGIN
 
 -- Combinational Process
-  p_comb : PROCESS(r, rst, snk_in, dp_pipeline_src_out, dp_fifo_sc_rd_emp)
+  p_comb : PROCESS(r, rst, snk_in, dp_pipeline_src_out, dp_fifo_sc_rd_emp, eth_src_mac)
     VARIABLE v : t_reg;
   BEGIN
     v := r;

libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd

@@ -64,7 +64,7 @@ BEGIN
   -------------------------------------------------
   -- process to calculate the ip_header_checksum --
   -------------------------------------------------
-  p_calc_chksum : PROCESS(clk)
+  p_calc_chksum : PROCESS(clk, rst)
   BEGIN
     IF rst = '1' THEN
       sum <= (OTHERS => '0');
@@ -99,7 +99,7 @@ BEGIN
   -- process to insert checksum in outgoing stream --
   --------------------------------------------------- 
   checksum <= NOT(STD_LOGIC_VECTOR(sum(c_halfword_w-1 DOWNTO 0)+sum(sum'HIGH DOWNTO c_halfword_w))); -- checksum = inverted (sum + carry)  
-  p_insert_chksum : PROCESS(dp_pipeline_src_out, checksum, count) 
+  p_insert_chksum : PROCESS(dp_pipeline_src_out, checksum, count_p) 
   BEGIN
     src_out <= dp_pipeline_src_out;
     IF TO_UINT(count_p) = 2 THEN