removed the mm interface for transceiver links for uniboard2b, should be in the uniboard2b library

boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd

@@ -55,8 +55,6 @@ ENTITY unb2_board_10gbe IS
     reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi   : IN  t_mem_mosi := c_mem_mosi_rst; 
     reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso   : OUT t_mem_miso;
 
-    reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi   : IN  t_mem_mosi := c_mem_mosi_rst; 
-    reg_ip_arria10_e1sg_phy_10gbase_r_24_miso   : OUT t_mem_miso;
     -- DP interface
     dp_rst              : IN  STD_LOGIC := '0';
     dp_clk              : IN  STD_LOGIC := '0';
@@ -123,8 +121,6 @@ BEGIN
 
       reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
       reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,      
-      reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi   => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi,
-      reg_ip_arria10_e1sg_phy_10gbase_r_24_miso   => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso,      
     
       -- DP interface
       dp_rst              => dp_rst,