-Cleaned code.

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -147,14 +147,6 @@ ARCHITECTURE rtl OF st_histogram IS
   SIGNAL nxt_bin_writer_mosi            : t_mem_mosi;
   SIGNAL bin_writer_mosi                : t_mem_mosi;
 
-  -------------------------------------------------------------------------------
-  -- bin_arbiter
-  -------------------------------------------------------------------------------
-  SIGNAL bin_writer_ram_pointer     : STD_LOGIC;
-  SIGNAL bin_reader_ram_pointer     : STD_LOGIC;
-  SIGNAL prv_bin_reader_ram_pointer : STD_LOGIC;
-
-
   -------------------------------------------------------------------------------
   -- 2x RAM (common_ram_r_w) instances
   -------------------------------------------------------------------------------
@@ -165,6 +157,10 @@ ARCHITECTURE rtl OF st_histogram IS
                                              nof_dat  => g_nof_bins,
                                              init_sl  => '0');
 
+  SIGNAL bin_writer_ram_pointer     : STD_LOGIC;
+  SIGNAL bin_reader_ram_pointer     : STD_LOGIC;
+  SIGNAL prv_bin_reader_ram_pointer : STD_LOGIC;
+
   SIGNAL common_ram_r_w_wr_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
   SIGNAL common_ram_r_w_rd_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0);
   SIGNAL common_ram_r_w_rd_miso_arr : t_mem_miso_arr(1 DOWNTO 0);