Removed stratix4 architecture for common_add_sub. Changed all uses for...

Removed stratix4 architecture for common_add_sub. Changed all uses for common_add_sub to rtl implementation.

libraries/base/common/tb/vhdl/tb_common_add_sub.vhd

@@ -65,7 +65,6 @@ ARCHITECTURE tb OF tb_common_add_sub IS
   SIGNAL out_result      : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);  -- combinatorial result
   SIGNAL result_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);  -- pipelined results
   SIGNAL result_rtl      : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
-  SIGNAL result_stratix4 : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
 
 BEGIN
 
@@ -145,7 +144,7 @@ BEGIN
     out_dat => result_expected
   );
   
-  u_dut_rtl : ENTITY work.common_add_sub(rtl)
+  u_dut_rtl : ENTITY work.common_add_sub
   GENERIC MAP (
     g_direction       => g_direction,
     g_representation  => "SIGNED",
@@ -163,30 +162,11 @@ BEGIN
     result  => result_rtl
   );
 
-  u_dut_stratix4 : ENTITY work.common_add_sub(stratix4)
-  GENERIC MAP (
-    g_direction       => g_direction,
-    g_representation  => "SIGNED",
-    g_pipeline_input  => g_pipeline_in,
-    g_pipeline_output => g_pipeline_out,
-    g_in_dat_w        => g_in_dat_w,
-    g_out_dat_w       => g_out_dat_w
-  )
-  PORT MAP (
-    clk     => clk,
-    clken   => '1',
-    sel_add => g_sel_add,
-    in_a    => in_a,
-    in_b    => in_b,
-    result  => result_stratix4
-  );
-  
   p_verify : PROCESS(rst, clk)
   BEGIN
     IF rst='0' THEN
       IF rising_edge(clk) THEN
         ASSERT result_rtl      = result_expected REPORT "Error: wrong RTL result" SEVERITY ERROR;
-        ASSERT result_stratix4 = result_expected REPORT "Error: wrong stratix4 result" SEVERITY ERROR;
       END IF;
     END IF;
   END PROCESS;