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Commit 4cc7a033 authored by Eric Kooistra's avatar Eric Kooistra
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Added functions for resizing to the mosi/miso record slv fields.

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libraries/technology/ddr/tech_ddr_pkg.vhd
+ 58
− 16
View file @ 4cc7a033
......@@ -55,8 +55,8 @@ PACKAGE tech_ddr_pkg IS
END RECORD;
FUNCTION func_tech_ddr_dq_address_w( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR address width for the DQ data at the PHY mts rate
FUNCTION func_tech_ddr_ctrl_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR address width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_ctrl_data_w( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR data width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR address width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_ctlr_data_w( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR data width for the controller data at the by rsl=4 reduced rate
FUNCTION func_tech_ddr_module_size( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR module size in GByte
CONSTANT c_tech_ddr_max : t_c_tech_ddr := ("none", 800, TRUE, 16, 16, 10, 3, 64, 8, 8, 2, 2, 2, 1, 2, 14, 4, 2, 64, 7); -- maximum ranges for record field definitions
......@@ -127,30 +127,42 @@ PACKAGE tech_ddr_pkg IS
FUNCTION func_tech_ddr_dq_address( dq_address : STD_LOGIC_VECTOR; g_tech_ddr : t_c_tech_ddr ) RETURN t_tech_ddr_addr;
FUNCTION func_tech_ddr_dq_address( ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_dq_address_w : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION func_tech_ddr_ctrl_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_ctrl_address_w : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION func_tech_ddr_ctlr_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_ctlr_address_w : NATURAL) RETURN STD_LOGIC_VECTOR;
-- PHY MM access signal record
CONSTANT c_tech_ddr_max_ctrl_address_w : NATURAL := 32; -- >= func_tech_ddr_ctrl_address_w(c_tech_ddr_max);
CONSTANT c_tech_ddr_max_ctrl_data_w : NATURAL := 576; -- >= func_tech_ddr_ctrl_data_w( c_tech_ddr_max);
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
CONSTANT c_tech_ddr_ctlr_address_w : NATURAL := 32; -- >= func_tech_ddr_ctlr_address_w(c_tech_ddr_max);
CONSTANT c_tech_ddr_ctlr_data_w : NATURAL := 576; -- >= func_tech_ddr_ctlr_data_w( c_tech_ddr_max);
CONSTANT c_tech_ddr_ctlr_burstsize_w : NATURAL := c_tech_ddr_max.maxburstsize_w;
TYPE t_tech_ddr_miso IS RECORD
rddata : STD_LOGIC_VECTOR(c_tech_ddr_max_ctrl_data_w-1 DOWNTO 0);
rddata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
rdval : STD_LOGIC;
waitrequest_n : STD_LOGIC;
END RECORD;
TYPE t_tech_ddr_mosi IS RECORD
address : STD_LOGIC_VECTOR(c_tech_ddr_max_ctrl_address_w-1 DOWNTO 0);
wrdata : STD_LOGIC_VECTOR(c_tech_ddr_max_ctrl_data_w-1 DOWNTO 0);
wr : STD_LOGIC;
rd : STD_LOGIC;
burstbegin : STD_LOGIC;
burstsize : STD_LOGIC_VECTOR(c_tech_ddr_max.maxburstsize_w-1 DOWNTO 0);
address : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_address_w-1 DOWNTO 0);
wrdata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
wr : STD_LOGIC;
rd : STD_LOGIC;
burstbegin : STD_LOGIC;
burstsize : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_burstsize_w-1 DOWNTO 0);
END RECORD;
CONSTANT c_tech_ddr_miso_rst : t_tech_ddr_miso := ((OTHERS=>'0'), '0', '0');
CONSTANT c_tech_ddr_mosi_rst : t_tech_ddr_mosi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', (OTHERS=>'0'));
-- Resize functions to fit an integer or an SLV in the corresponding t_tech_ddr_miso or t_tech_ddr_mosi field width
FUNCTION TO_DDR_CTLR_ADDRESS( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
FUNCTION TO_DDR_CTLR_DATA( n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION TO_DDR_CTLR_BURSTSIZE(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_DDR_CTLR_ADDRESS( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_DDR_CTLR_DATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_DDR_CTLR_BURSTSIZE(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
END tech_ddr_pkg;
PACKAGE BODY tech_ddr_pkg IS
......@@ -160,13 +172,13 @@ PACKAGE BODY tech_ddr_pkg IS
RETURN c_ddr.cs_w_w + c_ddr.ba_w + c_ddr.a_w + c_ddr.a_col_w;
END;
FUNCTION func_tech_ddr_ctrl_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
FUNCTION func_tech_ddr_ctlr_address_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
BEGIN
RETURN c_dq_address_w-c_ddr.rsl_w;
END;
FUNCTION func_tech_ddr_ctrl_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
FUNCTION func_tech_ddr_ctlr_data_w(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
BEGIN
RETURN c_ddr.dq_w*c_ddr.rsl;
......@@ -200,12 +212,42 @@ PACKAGE BODY tech_ddr_pkg IS
ddr_addr.col( g_tech_ddr.a_col_w-1 DOWNTO 0), c_dq_address_w);
END;
FUNCTION func_tech_ddr_ctrl_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_ctrl_address_w : NATURAL) RETURN STD_LOGIC_VECTOR IS
FUNCTION func_tech_ddr_ctlr_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_ctlr_address_w : NATURAL) RETURN STD_LOGIC_VECTOR IS
CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(g_tech_ddr);
CONSTANT c_dq_address : STD_LOGIC_VECTOR(c_dq_address_w-1 DOWNTO 0) := func_tech_ddr_dq_address(ddr_addr, g_tech_ddr, c_dq_address_w);
BEGIN
RETURN RESIZE_UVEC(c_dq_address(c_dq_address_w-1 DOWNTO g_tech_ddr.rsl_w), c_ctrl_address_w);
RETURN RESIZE_UVEC(c_dq_address(c_dq_address_w-1 DOWNTO g_tech_ddr.rsl_w), c_ctlr_address_w);
END;
FUNCTION TO_DDR_CTLR_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_tech_ddr_ctlr_address_w);
END TO_DDR_CTLR_ADDRESS;
FUNCTION TO_DDR_CTLR_DATA(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_tech_ddr_ctlr_data_w);
END TO_DDR_CTLR_DATA;
FUNCTION TO_DDR_CTLR_BURSTSIZE(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(TO_SVEC(n, 32), c_tech_ddr_ctlr_burstsize_w);
END TO_DDR_CTLR_BURSTSIZE;
FUNCTION RESIZE_DDR_CTLR_ADDRESS(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_tech_ddr_ctlr_address_w);
END RESIZE_DDR_CTLR_ADDRESS;
FUNCTION RESIZE_DDR_CTLR_DATA(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_tech_ddr_ctlr_data_w);
END RESIZE_DDR_CTLR_DATA;
FUNCTION RESIZE_DDR_CTLR_BURSTSIZE(vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN RESIZE_UVEC(vec, c_tech_ddr_ctlr_burstsize_w);
END RESIZE_DDR_CTLR_BURSTSIZE;
END tech_ddr_pkg;
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