post compilation temp and voltage sensors

libraries/io/fpga_sense/hdllib.cfg

-hdl_lib_name = fpga__sense
+hdl_lib_name = fpga_sense
 hdl_library_clause_name = fpga_sense_lib
 hdl_lib_uses_synth = common technology tech_fpga_temp_sens tech_fpga_voltage_sens
 hdl_lib_uses_sim = 

libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd

@@ -69,9 +69,17 @@ ARCHITECTURE str OF fpga_sense IS
   CONSTANT c_mem_reg_voltage_nof_data  : NATURAL := 1;
   CONSTANT c_mem_reg_voltage_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_voltage_adr_w , c_mem_reg_voltage_dat_w , c_mem_reg_voltage_nof_data, 'X');
 
-  SIGNAL mm_reg_temp_data : STD_LOGIC_VECTOR(c_mem_reg_dat_w-1 downto 0);
+  SIGNAL mm_reg_temp_data : STD_LOGIC_VECTOR(c_mem_reg_temp_dat_w-1 downto 0);
   SIGNAL temp_data        : STD_LOGIC_VECTOR(9 downto 0);
   SIGNAL eoc              : STD_LOGIC;
+  signal start_sense_mm : STD_LOGIC := '0';
+  signal start_sense_mm_d1 : STD_LOGIC := '0';
+  signal start_sense_mm_d2 : STD_LOGIC := '0';
+  signal controller_csr_write : STD_LOGIC := '0';
+  SIGNAL controller_csr_writedata : STD_LOGIC_VECTOR(31 downto 0) := X"00000001"; 
+                                        -- bits 9:8 = "00" select channels 2-7
+                                        -- bits 2:1 = "00" select single conversion
+                                        -- bit 0 = '1' set the self-clearing run bit 
 
 BEGIN
 
@@ -94,7 +102,7 @@ BEGIN
       IF mm_rst = '1' THEN
         mm_reg_temp_data <= (OTHERS => '0');
       ELSIF falling_edge(eoc) THEN
-        mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
+        mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
       END IF;
     END PROCESS;
 
@@ -106,7 +114,7 @@ BEGIN
                                                              
     temp_data <= TO_UVEC(460, temp_data'LENGTH);   -- choose temp = 45 degrees so adc temp_data = 460
     --temp_data <= RESIZE_UVEC(x"45",10);
-    mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
+    mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
   END GENERATE;
 
   u_reg_map : ENTITY common_lib.common_reg_r_w_dc
@@ -146,26 +154,33 @@ BEGIN
       )
       PORT MAP (
         clock_clk                  => mm_clk,
-        reset_sink_reset           => mm_reset,
-        controller_csr_address     => controller_csr_address,
-        controller_csr_read        => controller_csr_read,
+        reset_sink_reset           => mm_rst,
+        controller_csr_address     => '1',
+        controller_csr_read        => '0',
         controller_csr_write       => controller_csr_write,
         controller_csr_writedata   => controller_csr_writedata,
-        controller_csr_readdata    => controller_csr_readdata,
-        sample_store_csr_address   => reg_voltage_store_mosi.address,
-        sample_store_csr_read      => reg_voltage_store_mosi.read,
-        sample_store_csr_write     => reg_voltage_store_mosi.write,
-        sample_store_csr_writedata => reg_voltage_store_mosi.writedata,
-        sample_store_csr_readdata  => reg_voltage_store_mosi.readdata,
-        sample_store_irq_irq       => sample_store_irq_irq
+        controller_csr_readdata    => open,
+        sample_store_csr_address   => reg_voltage_store_mosi.address(3 downto 0),
+        sample_store_csr_read      => reg_voltage_store_mosi.rd,
+        sample_store_csr_write     => reg_voltage_store_mosi.wr,
+        sample_store_csr_writedata => reg_voltage_store_mosi.wrdata(31 downto 0),
+        sample_store_csr_readdata  => reg_voltage_store_miso.rddata(31 downto 0),
+        sample_store_irq_irq       => open
     );
 
     PROCESS(eoc, mm_rst)
       BEGIN
         IF mm_rst = '1' THEN
-          mm_reg_temp_data <= (OTHERS => '0');
-        ELSIF falling_edge(eoc) THEN
-          mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
+          controller_csr_write <= '0';
+        ELSIF rising_edge(mm_clk) THEN
+          start_sense_mm <= start_sense;
+          start_sense_mm_d1 <= start_sense_mm;
+          start_sense_mm_d2 <= start_sense_mm_d1;
+          if start_sense_mm_d1 = '1' and start_sense_mm_d2 = '0' then
+            controller_csr_write <= '1';
+	  else 
+            controller_csr_write <= '0';
+          end if;
         END IF;
     END PROCESS;
 

libraries/io/fpga_temp_sens/hdllib.cfg

-hdl_lib_name = fpga_temp_sens
-hdl_library_clause_name = fpga_temp_sens_lib
-hdl_lib_uses_synth = common technology tech_fpga_temp_sens
-hdl_lib_uses_sim = 
-
-hdl_lib_technology = 
-
-synth_files =
-    src/vhdl/fpga_temp_sens.vhd
-
-test_bench_files = 
-

libraries/io/fpga_temp_sens/src/vhdl/fpga_temp_sens.vhd

--------------------------------------------------------------------------------
---
--- Copyright (C) 2015
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose:
--- Description:
---  
-
-
-LIBRARY IEEE, common_lib, technology_lib, tech_fpga_temp_sens_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
---USE tech_temp_sense_lib.tech_temp_sense_component_pkg.ALL;
-
-
-ENTITY fpga_temp_sens IS
-  GENERIC (
-    g_technology     : NATURAL := c_tech_select_default;
-    g_sim            : BOOLEAN
-  );
-  PORT (
-    -- MM interface
-    mm_rst      : IN  STD_LOGIC;
-    mm_clk      : IN  STD_LOGIC;
-
-    start_sense : IN  STD_LOGIC;
-    
-    reg_mosi    : IN  t_mem_mosi := c_mem_mosi_rst;
-    reg_miso    : OUT t_mem_miso
-  );
-END fpga_temp_sens;
-
-
-ARCHITECTURE str OF fpga_temp_sens IS
-
-  CONSTANT c_mem_reg_adr_w     : NATURAL := 1;
-  CONSTANT c_mem_reg_dat_w     : NATURAL := 32;
-  CONSTANT c_mem_reg_nof_data  : NATURAL := 1;
-  CONSTANT c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_adr_w , c_mem_reg_dat_w , c_mem_reg_nof_data, 'X');
-
-  SIGNAL mm_reg_temp_data : STD_LOGIC_VECTOR(c_mem_reg_dat_w-1 downto 0);
-  SIGNAL temp_data        : STD_LOGIC_VECTOR(9 downto 0);
-  SIGNAL eoc              : STD_LOGIC;
-
-BEGIN
-
-  gen_tech_fpga_temp_sens: IF g_sim=FALSE GENERATE
-    u_tech_fpga_temp_sens : ENTITY tech_fpga_temp_sens_lib.tech_fpga_temp_sens
-    GENERIC MAP (
-      g_technology => g_technology
-    )
-    PORT MAP (
-      corectl => start_sense,
-      eoc     => eoc,      --: OUT STD_LOGIC;
-      reset   => mm_rst,
-      tempout => temp_data --: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
-    );
-
-    PROCESS(eoc, mm_rst)
-    BEGIN
-      IF mm_rst = '1' THEN
-        mm_reg_temp_data <= (OTHERS => '0');
-      ELSIF falling_edge(eoc) THEN
-        mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
-      END IF;
-    END PROCESS;
-
-  END GENERATE;
-
-
-
-  gen_no_tech_fpga_temp_sens: IF g_sim=TRUE GENERATE
-    -- temp = (708 * adc)/1024 - 273 => adc = (temp + 273)*1024/708
-    temp_data <= TO_UVEC(460, temp_data'LENGTH);   -- choose temp = 45 degrees so adc temp_data = 460
-    mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_dat_w);
-  END GENERATE;
-
-
-
-
-
-
-
-  u_reg_map : ENTITY common_lib.common_reg_r_w_dc
-  GENERIC MAP (
-    g_cross_clock_domain => FALSE,
-    g_in_new_latency     => 0,
-    g_readback           => FALSE,
-    g_reg                => c_mem_reg_temp_data,
-    g_init_reg           => (OTHERS => '0')
-  )
-  PORT MAP (
-    -- Clocks and reset
-    mm_rst      => mm_rst,
-    mm_clk      => mm_clk,
-    st_rst      => mm_rst,
-    st_clk      => mm_clk,
-
-    -- Memory Mapped Slave in mm_clk domain
-    sla_in      => reg_mosi,
-    sla_out     => reg_miso,
-
-    -- MM registers in st_clk domain
-    reg_wr_arr  => OPEN,
-    reg_rd_arr  => OPEN,
-    in_new      => '1',
-    in_reg      => mm_reg_temp_data,
-    out_reg     => OPEN
-  );
-END str;