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Commit 4c65a07e authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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update on 10GbE channels

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boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+ 184
− 102
View file @ 4c65a07e
......@@ -45,7 +45,11 @@ ENTITY unb2_test IS
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_factory_image : BOOLEAN := FALSE;
g_nof_streams_qsfp : NATURAL := 1; --FIXME
g_nof_streams_ring : NATURAL := 0; --FIXME
g_nof_streams_back : NATURAL := 0 --FIXME
);
PORT (
-- GENERAL
......@@ -108,7 +112,7 @@ ENTITY unb2_test IS
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_RST : INOUT STD_LOGIC;
QSFP_LED : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)
);
END unb2_test;
......@@ -124,7 +128,7 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_lpbk : BOOLEAN := FALSE; --g_design_name = "unb2_test_lpbk";
CONSTANT c_use_1GbE : BOOLEAN := FALSE; --g_design_name = "unb2_test_1GbE";
CONSTANT c_use_10GbE : BOOLEAN := TRUE; --g_design_name = "unb2_test_10GbE";
CONSTANT c_nof_streams : NATURAL := 1; --c_unb2_board_tr_qsfp_hw_nof_lines; --FIXME
CONSTANT g_nof_streams : NATURAL := (g_nof_streams_qsfp + g_nof_streams_ring + g_nof_streams_back);
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_lpbk, c_lpbk_data_w, -- Select correct c_data_w when one interface is used
sel_a_b(c_use_1GbE, c_eth_data_w,
sel_a_b(c_use_10GbE, c_xgmii_data_w, 0)));
......@@ -198,8 +202,8 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_max_nof_blocks_per_packet : NATURAL := c_max_udp_payload_nof_words/c_min_nof_words_per_block;
CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL hdr_fields_in_arr : t_slv_1024_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL hdr_fields_out_arr : t_slv_1024_arr(g_nof_streams-1 DOWNTO 0);
-- System
......@@ -264,10 +268,17 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_remu_miso : t_mem_miso;
-- 10GbE
SIGNAL serial_10G_tx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 downto 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_hw_nof_lines-1 downto 0);
SIGNAL i_serial_10G_tx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
SIGNAL i_serial_10G_rx_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0);
SIGNAL i_serial_10G_tx_qsfp_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0);
SIGNAL i_serial_10G_rx_qsfp_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp+g_nof_streams_ring-1 DOWNTO 0);
SIGNAL i_serial_10G_tx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0);
SIGNAL i_serial_10G_rx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0);
SIGNAL serial_10G_tx_qsfp_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_qsfp_arr : STD_LOGIC_VECTOR(g_nof_streams_qsfp * c_unb2_board_tr_qsfp.bus_w-1 DOWNTO 0);
SIGNAL serial_10G_tx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_ring_arr : STD_LOGIC_VECTOR(g_nof_streams_ring-1 DOWNTO 0);
SIGNAL serial_10G_tx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL serial_10G_rx_back_arr : STD_LOGIC_VECTOR(g_nof_streams_back-1 DOWNTO 0);
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso;
......@@ -303,26 +314,33 @@ ARCHITECTURE str OF unb2_test IS
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL block_gen_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL tmp_dp_offload_tx_src_out_arr : t_dp_sosi_arr(4*g_nof_streams-1 DOWNTO 0);
SIGNAL tmp_dp_offload_tx_src_in_arr : t_dp_siso_arr(4*g_nof_streams-1 DOWNTO 0);
SIGNAL tmp_dp_offload_rx_snk_in_arr : t_dp_sosi_arr(4*g_nof_streams-1 DOWNTO 0);
SIGNAL user_green_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL user_red_led_arr : STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-- Interface: 1GbE UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
BEGIN
......@@ -343,8 +361,9 @@ BEGIN
g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
g_aux => c_unb2_board_aux,
g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams,
g_dp_clk_use_pll => TRUE
g_udp_offload_nof_streams => g_nof_streams,
g_dp_clk_use_pll => TRUE,
g_factory_image => g_factory_image
)
PORT MAP (
-- Clock an reset signals
......@@ -448,7 +467,7 @@ BEGIN
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_nof_streams => 3, --c_nof_streams, --FIXME
g_nof_streams => 3, --g_nof_streams, --FIXME
g_bg_block_size => c_bg_block_size,
g_hdr_field_arr => c_hdr_field_arr
)
......@@ -550,7 +569,7 @@ BEGIN
-----------------------------------------------------------------------------
u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP (
g_nof_output_streams => c_nof_streams,
g_nof_output_streams => g_nof_streams,
g_buf_dat_w => c_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(c_data_w),
......@@ -577,7 +596,7 @@ BEGIN
-----------------------------------------------------------------------------
u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx_dev
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_nof_streams => g_nof_streams,
g_data_w => c_data_w,
g_use_complex => FALSE,
g_max_nof_words_per_block => c_max_nof_words_per_block,
......@@ -613,7 +632,7 @@ BEGIN
hdr_fields_in_arr => hdr_fields_in_arr
);
gen_hdr_in_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
gen_hdr_in_fields : FOR i IN 0 TO g_nof_streams-1 GENERATE
-- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac")) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
......@@ -636,7 +655,7 @@ BEGIN
-----------------------------------------------------------------------------
u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx_dev
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_nof_streams => g_nof_streams,
g_data_w => c_data_w,
g_hdr_field_arr => c_hdr_field_arr,
g_remove_crc => NOT(c_use_lpbk),
......@@ -661,7 +680,7 @@ BEGIN
hdr_fields_out_arr => hdr_fields_out_arr
);
gen_hdr_out_fields : FOR i IN 0 TO c_nof_streams-1 GENERATE
gen_hdr_out_fields : FOR i IN 0 TO g_nof_streams-1 GENERATE
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
END GENERATE;
......@@ -674,7 +693,7 @@ BEGIN
-----------------------------------------------------------------------------
dp_offload_rx_src_in_arr <= diag_data_buf_snk_out_arr;
gen_bsn_mon_in : FOR i IN 0 TO c_nof_streams-1 GENERATE
gen_bsn_mon_in : FOR i IN 0 TO g_nof_streams-1 GENERATE
diag_data_buf_snk_in_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
diag_data_buf_snk_in_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
diag_data_buf_snk_in_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
......@@ -684,7 +703,7 @@ BEGIN
u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_nof_streams => g_nof_streams,
g_cross_clock_domain => TRUE,
g_sync_timeout => c_bg_blocks_per_sync*(c_bg_block_size+c_bg_gapsize),
g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync+1),
......@@ -707,7 +726,7 @@ BEGIN
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_nof_streams,
g_nof_streams => g_nof_streams,
g_data_w => 32, --c_data_w,
g_buf_nof_data => 1024,
g_buf_use_sync => FALSE -- sync by reading last address of data buffer
......@@ -754,12 +773,12 @@ BEGIN
-- tr_10GbE
-----------------------------------------------------------------------------
gen_tr_10GbE : IF c_use_10GbE=TRUE GENERATE
u_tr_10GbE_front_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe_front_and_ring
u_tr_10GbE_qsfp_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe
GENERIC MAP (
g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => c_nof_streams,
g_nof_macs => (g_nof_streams_qsfp + g_nof_streams_ring),
g_tx_fifo_fill => c_def_10GbE_block_size,
g_tx_fifo_size => c_def_10GbE_block_size*2
)
......@@ -777,74 +796,142 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
src_out_arr => dp_offload_rx_snk_in_arr,
src_in_arr => dp_offload_rx_snk_out_arr,
src_out_arr => dp_offload_rx_snk_in_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
src_in_arr => dp_offload_rx_snk_out_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
snk_out_arr => dp_offload_tx_src_in_arr,
snk_in_arr => dp_offload_tx_src_out_arr,
snk_out_arr => dp_offload_tx_src_in_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
snk_in_arr => dp_offload_tx_src_out_arr((g_nof_streams_qsfp+g_nof_streams_ring-1) DOWNTO 0),
-- Serial IO
serial_tx_arr => i_serial_10G_tx_arr,
serial_rx_arr => i_serial_10G_rx_arr
serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
);
-- u_tr_10GbE_back: ENTITY unb2_board_lib.unb2_board_10gbe
-- GENERIC MAP (
-- g_technology => g_technology,
-- g_sim => g_sim,
-- g_sim_level => 1,
-- g_nof_macs => g_nof_streams_back,
-- g_tx_fifo_fill => c_def_10GbE_block_size,
-- g_tx_fifo_size => c_def_10GbE_block_size*2
-- )
-- PORT MAP (
-- tr_ref_clk => SB_CLK,
--
-- -- MM interface
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
--
-- reg_mac_mosi => reg_tr_10GbE_mosi, -- FIXME use separate
-- reg_mac_miso => reg_tr_10GbE_miso,
--
-- -- DP interface
-- dp_rst => dp_rst,
-- dp_clk => dp_clk,
--
-- src_out_arr => dp_offload_rx_snk_in_arr((g_nof_streams_back-1) DOWNTO 0),
-- src_in_arr => dp_offload_rx_snk_out_arr((g_nof_streams_back-1) DOWNTO 0),
--
-- snk_out_arr => dp_offload_tx_src_in_arr((g_nof_streams_back-1) DOWNTO 0),
-- snk_in_arr => dp_offload_tx_src_out_arr((g_nof_streams_back-1) DOWNTO 0),
--
-- -- Serial IO
-- serial_tx_arr => i_serial_10G_tx_back_arr,
-- serial_rx_arr => i_serial_10G_rx_back_arr
-- );
gen_wires: FOR i IN 0 TO c_nof_streams-1 GENERATE
serial_10G_tx_arr(i) <= i_serial_10G_tx_arr(i);
i_serial_10G_rx_arr(i) <= serial_10G_rx_arr(i);
END GENERATE;
serial_10G_tx_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO c_nof_streams) <= (OTHERS=>'0');
--gen_wires: FOR i IN 0 TO g_nof_streams_qsfp-1 GENERATE
-- serial_10G_tx_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
-- i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_arr(i);
--END GENERATE;
serial_10G_tx_qsfp_arr(0) <= i_serial_10G_tx_qsfp_ring_arr(0);
i_serial_10G_rx_qsfp_ring_arr(0) <= serial_10G_rx_qsfp_arr(0);
--serial_10G_tx_qsfp_arr(c_unb2_board_tr_qsfp_hw_nof_lines-1 DOWNTO g_nof_streams) <= (OTHERS=>'0');
u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
GENERIC MAP (
g_nof_qsfp_bus => ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w)
)
PORT MAP (
serial_tx_arr => serial_10G_tx_arr,
serial_rx_arr => serial_10G_rx_arr,
serial_tx_arr => serial_10G_tx_qsfp_arr,
serial_rx_arr => serial_10G_rx_qsfp_arr,
green_led_arr => user_green_led_arr(g_nof_streams_qsfp-1 DOWNTO 0),
red_led_arr => user_red_led_arr(g_nof_streams_qsfp-1 DOWNTO 0),
-- Serial I/O
-- front transceivers
QSFP_0_RX => QSFP_0_RX,
QSFP_0_TX => QSFP_0_TX,
-- QSFP_1_RX => QSFP_1_RX,
-- QSFP_1_TX => QSFP_1_TX,
-- QSFP_2_RX => QSFP_2_RX,
-- QSFP_2_TX => QSFP_2_TX,
-- QSFP_3_RX => QSFP_3_RX,
-- QSFP_3_TX => QSFP_3_TX,
-- QSFP_4_RX => QSFP_4_RX,
-- QSFP_4_TX => QSFP_4_TX,
-- QSFP_5_RX => QSFP_5_RX,
-- QSFP_5_TX => QSFP_5_TX,
QSFP_RX(0)(0) => QSFP_0_RX(0),
QSFP_TX(0)(0) => QSFP_0_TX(0),
QSFP_SDA => QSFP_SDA,
QSFP_SCL => QSFP_SCL,
QSFP_RST => QSFP_RST,
QSFP_LED => QSFP_LED
);
tmp_dp_offload_tx_src_out_arr(0) <= dp_offload_tx_src_out_arr(0);
tmp_dp_offload_tx_src_in_arr(0) <= dp_offload_tx_src_in_arr(0);
tmp_dp_offload_rx_snk_in_arr(0) <= dp_offload_rx_snk_in_arr(0);
u_front_led : ENTITY work.unb2_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => ceil_div(g_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w),
g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- internal pulser outputs
--pulse_us => pulse_us,
--pulse_ms => pulse_ms,
--pulse_s => pulse_s,
-- lane status
tx_siso_arr => tmp_dp_offload_tx_src_in_arr,--(g_nof_streams_qsfp-1 DOWNTO 0),
tx_sosi_arr => tmp_dp_offload_tx_src_out_arr,--(g_nof_streams_qsfp-1 DOWNTO 0),
rx_sosi_arr => tmp_dp_offload_rx_snk_in_arr,--(g_nof_streams_qsfp-1 DOWNTO 0),
-- leds
green_led_arr => user_green_led_arr(g_nof_streams_qsfp-1 DOWNTO 0),
red_led_arr => user_red_led_arr(g_nof_streams_qsfp-1 DOWNTO 0)
);
-- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
-- GENERIC MAP (
-- g_nof_back_io => g_nof_streams_back
-- )
-- PORT MAP (
-- serial_tx_arr => (OTHERS=>'0'),
-- --serial_rx_arr => ,
-- serial_tx_arr => serial_10G_tx_back_arr,
-- serial_rx_arr => serial_10G_rx_back_arr,
--
-- -- Serial I/O
-- -- back transceivers
-- BCK_RX => BCK_RX,
-- BCK_TX => BCK_TX,
--
-- BCK_SDA => BCK_SDA,
-- BCK_SCL => BCK_SCL,
-- BCK_ERR => BCK_ERR
-- );
--
-- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
-- GENERIC MAP (
-- g_nof_ring_io => g_nof_streams_ring
-- )
-- PORT MAP (
-- serial_tx_arr => (OTHERS=>'0'),
-- --serial_rx_arr => ,
-- serial_tx_arr => serial_10G_tx_ring_arr,
-- serial_rx_arr => serial_10G_rx_ring_arr,
--
-- -- Serial I/O
-- -- ring transceivers
-- RING_0_RX => RING_0_RX,
......@@ -854,10 +941,5 @@ BEGIN
-- );
END GENERATE;
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
-- Insert node_[design_name] here
END str;
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