L2SDP-206, processed review comment

applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd

@@ -275,7 +275,7 @@ ARCHITECTURE str OF lofar2_unb2b_filterbank IS
 
   -- Statistics ??
   SIGNAL id_backplane               : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
-  SIGNAL id_eth                     : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+  SIGNAL id_chip                    : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
 
   SIGNAL udp_tx_sosi_arr            : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
   SIGNAL udp_tx_siso_arr            : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0);  
@@ -321,6 +321,7 @@ BEGIN
     g_protect_addr_range      => g_protect_addr_range,
     g_dp_clk_freq             => c_dp_clk_freq,
     g_dp_clk_use_pll          => FALSE,
+    g_udp_offload             => TRUE,
     g_udp_offload_nof_streams => c_eth_nof_udp_ports
   )
   PORT MAP (
@@ -628,10 +629,12 @@ BEGIN
 
   -- derive MAC, IP and UDP Port from ID
   id_backplane <= RESIZE_UVEC(ID(c_sdp_W_gn_id-1 DOWNTO 2), c_byte_w);
-  id_eth       <= RESIZE_UVEC(ID(1 DOWNTO 0) & TO_UVEC(0, 2), c_byte_w);  
-  eth_src_mac  <= c_sdp_cep_eth_src_mac_47_16 & id_backplane & INCR_UVEC(id_eth, 0); -- Interface id = 0
-  ip_src_addr  <= c_sdp_cep_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_eth, 1);     -- Interface id = 0
-  udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+  id_chip      <= RESIZE_UVEC(ID(1 DOWNTO 0), c_byte_w);   -- Unb2 has 4 FPGA chips
+
+  -- The eth_src_mac and ip_src_addr for SST offload are the same as for M&C, because they share the same 1GbE interface
+  eth_src_mac  <= c_sdp_stat_eth_src_mac_47_16 & id_backplane & id_chip;
+  ip_src_addr  <= c_sdp_stat_ip_src_addr_31_16 & id_backplane & INCR_UVEC(id_chip, 1);   -- +1, because IP address must be > 0
+  udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
 
   u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank 
   GENERIC MAP(

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd

@@ -60,8 +60,8 @@ ENTITY node_sdp_filterbank IS
     in_sosi_arr   : IN  t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
     pfb_sosi_arr  : OUT t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
     fsub_sosi_arr : OUT t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
-    sst_udp_siso  : IN  t_dp_siso := c_dp_siso_rst;
     sst_udp_sosi  : OUT t_dp_sosi;
+    sst_udp_siso  : IN  t_dp_siso := c_dp_siso_rst;
 
     mm_rst        : IN  STD_LOGIC;
     mm_clk        : IN  STD_LOGIC;
@@ -106,8 +106,8 @@ ARCHITECTURE str OF node_sdp_filterbank IS
   SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
   SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
   
-  SIGNAL ram_mem_mux_mosi    : t_mem_mosi := c_mem_mosi_rst;
-  SIGNAL ram_mem_mux_miso    : t_mem_miso := c_mem_miso_rst;
+  SIGNAL master_mem_mux_mosi    : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL master_mem_mux_miso    : t_mem_miso := c_mem_miso_rst;
   SIGNAL master_mosi_arr     : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
   SIGNAL master_miso_arr     : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
 
@@ -260,30 +260,30 @@ BEGIN
     g_mult_addr_w => ceil_log2(c_sdp_N_sub*c_sdp_Q_fft*g_wpfb.stat_data_sz)
   )
   PORT MAP (
-    mosi     => ram_mem_mux_mosi,
-    miso     => ram_mem_mux_miso,
+    mosi     => master_mem_mux_mosi,
+    miso     => master_mem_mux_miso,
     mosi_arr => ram_st_sst_mosi_arr,
     miso_arr => ram_st_sst_miso_arr
   );
 
   -- Connect 2 mm_masters to the common_mem_mux output
-  master_mosi_arr(0)  <= ram_st_sst_mosi;
+  master_mosi_arr(0)  <= ram_st_sst_mosi;    -- MM access via QSYS MM bus
   ram_st_sst_miso     <= master_miso_arr(0);
-  master_mosi_arr(1)  <= ram_st_offload_mosi;
+  master_mosi_arr(1)  <= ram_st_offload_mosi;   -- MM access by SST offload
   ram_st_offload_miso <= master_miso_arr(1);
 
   u_mem_master_mux : ENTITY mm_lib.mm_master_mux
   GENERIC MAP (
     g_nof_masters    => c_nof_masters,
-    g_rd_latency_min => 2  -- TODO, make constant and check if value is right
+    g_rd_latency_min => 3  -- TODO, make constant and check if value is right
   )
   PORT MAP (
     mm_clk => mm_clk,
 
     master_mosi_arr => master_mosi_arr,
     master_miso_arr => master_miso_arr,
-    mux_mosi        => ram_mem_mux_mosi,
-    mux_miso        => ram_mem_mux_miso
+    mux_mosi        => master_mem_mux_mosi,
+    mux_miso        => master_mem_mux_miso
   );
   
   ---------------------------------------------------------------
@@ -310,8 +310,7 @@ BEGIN
   u_sdp_sst_udp_offload: ENTITY work.sdp_statistics_offload
   GENERIC MAP (
     g_statistics_type => "SST",
-    g_offload_time    => g_offload_time,
-    g_beamset_id      => 0
+    g_offload_time    => g_offload_time
   )
   PORT MAP (
     mm_clk    => mm_clk,

applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd

@@ -208,6 +208,18 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_reg_nw_10GbE_eth10g_addr_w : NATURAL := 1;
 
   -- statistics offload
+  -- The statistics offload uses the same 1GbE port as the NiosII for M&C. The 1GbE addresses defined in SW and here in FW.
+  -- See NiosII code:
+  --   https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
+  --   https://git.astron.nl/desp/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
+  -- and g_base_ip = x"0A63" in:
+  --   https://git.astron.nl/desp/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+
+  CONSTANT c_sdp_stat_eth_src_mac_47_16 : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00228608";  -- 00:22:86:08:pp:qq
+  CONSTANT c_sdp_stat_ip_src_addr_31_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0A63";    -- 10.99.xx.yy
+  CONSTANT c_sdp_sst_udp_src_port_15_8  : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D0";  -- TBC
+  CONSTANT c_sdp_bst_udp_src_port_15_8  : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D1";  -- TBC
+  CONSTANT c_sdp_xst_udp_src_port_15_8  : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D2";  -- TBC
 
   CONSTANT c_sdp_stat_nof_hdr_fields : NATURAL := 3+12+4+20+1; -- 592b; 9.25 64b words
   CONSTANT c_sdp_stat_hdr_field_sel  : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"01000000000000000000"&"0";  -- 0=data path, 1=MM controlled TODO
@@ -262,6 +274,7 @@ PACKAGE sdp_pkg is
   );
   CONSTANT c_sdp_reg_stat_hdr_dat_addr_w         : NATURAL := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
 
+
 END PACKAGE sdp_pkg;
 
 PACKAGE BODY sdp_pkg IS

applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd

@@ -76,14 +76,15 @@ BEGIN
   -- to be applied according the subband data order 
   -- fsub[S_pn/Q_fft]_[N_sub][Q_fft]. Therefore the counter in 
   -- sdp_subband_equalizer.vhd has to account for this difference in order.
-  p_cnt : PROCESS(dp_clk, dp_rst, in_sosi_arr)
+  p_cnt : PROCESS(dp_clk, dp_rst)
     VARIABLE v_Q_fft, v_N_sub : NATURAL;
   BEGIN
     IF dp_rst = '1' THEN
       cnt <= 0;
       v_Q_fft := 0;
       v_N_sub := 0;
-    ELSIF rising_edge(dp_clk) AND in_sosi_arr(0).valid = '1' THEN
+    ELSIF rising_edge(dp_clk) THEN
+      IF in_sosi_arr(0).valid = '1' THEN
         IF in_sosi_arr(0).eop = '1' THEN
           v_Q_fft := 0;
           v_N_sub := 0;
@@ -101,6 +102,7 @@ BEGIN
         END IF;
         cnt <= v_Q_fft * c_sdp_N_sub + v_N_sub;
       END IF;
+    END IF;
   END PROCESS;
   gains_rd_address <= TO_UVEC(cnt, c_gain_addr_w);