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Commit 4ba76893 authored by Pieter Donker's avatar Pieter Donker
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L2SD-515, updated mmap gold files

parent 7da83c34
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1 merge request!187Resolve L2SDP-515
Pipeline #23389 passed
Stage: simulation
Stage: synthesis
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boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold
+ 31
− 14
View file @ 4ba76893
......@@ -500,12 +500,16 @@ number_of_columns = 13
REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00c00000 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00c00000 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00c00000 1 RO uint32 b[3:2] - - -
REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00c80000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00c80001 1 WO uint32 b[0:0] - - -
- - - - done 0x00c80002 1 RO uint32 b[0:0] - - -
- - - - address 0x00c80005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00c80006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00c80007 1 RW uint32 b[0:0] - - -
REG_IO_DDR_MB_I 1 1 REG reg_io_ddr 0x00c80000 1 RO uint32 b[31:0] - - -
- - - - reg_rd_fifo_used 0x00c80001 1 RO uint32 b[31:0] - - -
- - - - reg_wr_fifo_used 0x00c80002 1 RO uint32 b[31:0] - - -
- - - - reg_fifo_full 0x00c80003 1 RO uint32 b[31:0] - - -
- - - - reg_burstbegin 0x00c80008 1 WO uint32 b[31:0] - - -
- - - - reg_wr_not_rd 0x00c80009 1 WO uint32 b[31:0] - - -
- - - - reg_done 0x00c8000a 1 RO uint32 b[31:0] - - -
- - - - reg_address 0x00c8000d 1 WO uint32 b[31:0] - - -
- - - - reg_burstsize 0x00c8000e 1 WO uint32 b[31:0] - - -
- - - - reg_flush 0x00c8000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00d00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00d00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00d00002 1 RO uint32 b[31:0] - - -
......@@ -521,12 +525,16 @@ number_of_columns = 13
REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00e00000 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00e00001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00e00400 1024 RW uint32 b[31:0] - - -
REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00e80000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00e80001 1 WO uint32 b[0:0] - - -
- - - - done 0x00e80002 1 RO uint32 b[0:0] - - -
- - - - address 0x00e80005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00e80006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00e80007 1 RW uint32 b[0:0] - - -
REG_IO_DDR_MB_II 1 1 REG reg_io_ddr 0x00e80000 1 RO uint32 b[31:0] - - -
- - - - reg_rd_fifo_used 0x00e80001 1 RO uint32 b[31:0] - - -
- - - - reg_wr_fifo_used 0x00e80002 1 RO uint32 b[31:0] - - -
- - - - reg_fifo_full 0x00e80003 1 RO uint32 b[31:0] - - -
- - - - reg_burstbegin 0x00e80008 1 WO uint32 b[31:0] - - -
- - - - reg_wr_not_rd 0x00e80009 1 WO uint32 b[31:0] - - -
- - - - reg_done 0x00e8000a 1 RO uint32 b[31:0] - - -
- - - - reg_address 0x00e8000d 1 WO uint32 b[31:0] - - -
- - - - reg_burstsize 0x00e8000e 1 WO uint32 b[31:0] - - -
- - - - reg_flush 0x00e8000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00f00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00f00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00f00002 1 RO uint32 b[31:0] - - -
......@@ -544,7 +552,16 @@ number_of_columns = 13
RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x01000400 1024 RW uint32 b[31:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x01080000 1 RW uint32 b[30:0] - - -
- - - - reset 0x01080000 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x01100014 1 RW uint32 b[16:0] - - 256
JESD204B 1 12 REG rx_lane_ctrl_common 0x01100000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x01100001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x01100002 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_2 0x01100003 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_3 0x01100004 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_4 0x01100005 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_5 0x01100006 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_6 0x01100007 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_7 0x01100008 1 RW uint32 b[2:0] - - -
- - - - rx_dll_ctrl 0x01100014 1 RW uint32 b[16:0] - - -
- - - - rx_syncn_sysref_ctrl 0x01100015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x01100015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x01100015 1 RW uint32 b[10:3] - - -
......
boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold
+ 31
− 14
View file @ 4ba76893
......@@ -500,12 +500,16 @@ number_of_columns = 13
REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00000c80 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00000c80 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00000c80 1 RO uint32 b[3:2] - - -
REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00160000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00160001 1 WO uint32 b[0:0] - - -
- - - - done 0x00160002 1 RO uint32 b[0:0] - - -
- - - - address 0x00160005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00160006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00160007 1 RW uint32 b[0:0] - - -
REG_IO_DDR_MB_I 1 1 REG reg_io_ddr 0x00160000 1 RO uint32 b[31:0] - - -
- - - - reg_rd_fifo_used 0x00160001 1 RO uint32 b[31:0] - - -
- - - - reg_wr_fifo_used 0x00160002 1 RO uint32 b[31:0] - - -
- - - - reg_fifo_full 0x00160003 1 RO uint32 b[31:0] - - -
- - - - reg_burstbegin 0x00160008 1 WO uint32 b[31:0] - - -
- - - - reg_wr_not_rd 0x00160009 1 WO uint32 b[31:0] - - -
- - - - reg_done 0x0016000a 1 RO uint32 b[31:0] - - -
- - - - reg_address 0x0016000d 1 WO uint32 b[31:0] - - -
- - - - reg_burstsize 0x0016000e 1 WO uint32 b[31:0] - - -
- - - - reg_flush 0x0016000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00000db8 1 RW uint32 b[2:0] - - -
- - - - init 0x00000db9 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000dba 1 RO uint32 b[31:0] - - -
......@@ -521,12 +525,16 @@ number_of_columns = 13
REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00000cc0 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00000cc1 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00003800 1024 RW uint32 b[31:0] - - -
REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00010000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00010001 1 WO uint32 b[0:0] - - -
- - - - done 0x00010002 1 RO uint32 b[0:0] - - -
- - - - address 0x00010005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00010006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00010007 1 RW uint32 b[0:0] - - -
REG_IO_DDR_MB_II 1 1 REG reg_io_ddr 0x00010000 1 RO uint32 b[31:0] - - -
- - - - reg_rd_fifo_used 0x00010001 1 RO uint32 b[31:0] - - -
- - - - reg_wr_fifo_used 0x00010002 1 RO uint32 b[31:0] - - -
- - - - reg_fifo_full 0x00010003 1 RO uint32 b[31:0] - - -
- - - - reg_burstbegin 0x00010008 1 WO uint32 b[31:0] - - -
- - - - reg_wr_not_rd 0x00010009 1 WO uint32 b[31:0] - - -
- - - - reg_done 0x0001000a 1 RO uint32 b[31:0] - - -
- - - - reg_address 0x0001000d 1 WO uint32 b[31:0] - - -
- - - - reg_burstsize 0x0001000e 1 WO uint32 b[31:0] - - -
- - - - reg_flush 0x0001000f 1 RW uint32 b[31:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00000db4 1 RW uint32 b[2:0] - - -
- - - - init 0x00000db5 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00000db6 1 RO uint32 b[31:0] - - -
......@@ -544,7 +552,16 @@ number_of_columns = 13
RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x00003000 1024 RW uint32 b[31:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x00000c02 1 RW uint32 b[30:0] - - -
- - - - reset 0x00000c02 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x00002014 1 RW uint32 b[16:0] - - 256
JESD204B 1 12 REG rx_lane_ctrl_common 0x00002000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00002001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00002002 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_2 0x00002003 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_3 0x00002004 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_4 0x00002005 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_5 0x00002006 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_6 0x00002007 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_7 0x00002008 1 RW uint32 b[2:0] - - -
- - - - rx_dll_ctrl 0x00002014 1 RW uint32 b[16:0] - - -
- - - - rx_syncn_sysref_ctrl 0x00002015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x00002015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x00002015 1 RW uint32 b[10:3] - - -
......
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