Skip to content
Snippets Groups Projects
Commit 49b268ed authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Remove ip/ level and ip_arria10_tse_sgmii_lvds_top.vhd wrapper.

parent 66cfd88c
No related branches found
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
Showing
with 18 additions and 167 deletions
libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+ 9
− 23
View file @ 49b268ed
......@@ -52,31 +52,17 @@ is included in the ip/hdllib.cfg and contains what is needed to synthesize the I
5) Remarks
a) Generated ip_arria10_tse_sgmii_lvds.vhd uses IP specific library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
a) Use generated IP specific library clause name
The generated ip_arria10_tse_sgmii_lvds.vhd uses library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140. This library needs to be vmap-ed
in every design that uses this IP. Therefore to make this library known created it in the ./ip directory with its own hdllib.cfg. The
ip/hdllib.cfg defines the IP library:
The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
specific library as library claus name to make it known:
hdl_lib_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
hdl_lib_name = ip_arria10_<lib_name>
hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
The ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library name is IP specific. The tech_tse/ library should not need to know about it, so
therefore use the ip_arria10_tse_sgmii_lvds_top.vhd wrapper in ip_arria10_tse_sgmii_lvds_lib that merely instantiates the IP. The
ip_arria10_tse_sgmii_lvds_top.vhd wrapper makes the IP accessible via ip_arria10_tse_sgmii_lvds_lib, to avoid that the IP specific library
needs to be used at the technology independent level.
An alternative would be to directly instantiate the generated IP ip_arria10_tse_sgmii_lvds.vhd in tech_tse_arria10.vhd, but then the
ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 also needs to be vmap-ped for the tech_tse library. This vmap could be done with a map_ip.tcl
script at the modelsim_compile_ip_files key containing:
vmap ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 $HDL_BUILD_DIR/modelsim/ip_arria10_tse_sgmii_lvds/work
However it is preferred not to bother the tech_tse library with such IP level details, so therefore using a seperate ./ip/hdllib.cfg and
the ip_arria10_tse_sgmii_lvds_top.vhd wrapper is deemed a better solution.
b) Generated IP uses several more libraries
The generated IP uses several more libraries. Just as the ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library these other libraries are
all mapped to ./work in ip/compile_ip.tcl.
The generated IP uses several more libraries. Just as the ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library
these other libraries are all mapped to ./work in ip/compile_ip.tcl.
\ No newline at end of file
libraries/technology/ip_arria10/tse_sgmii_lvds/ip/compile_ip.tcl → libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+ 1
− 1
View file @ 49b268ed
......@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/generated/sim"
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
#vlib ./work/ ;# Assume library work already exists
......
libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+ 3
− 4
View file @ 49b268ed
hdl_lib_name = ip_arria10_tse_sgmii_lvds
hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_lib
hdl_lib_uses = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 common
hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
hdl_lib_uses = common
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
ip_arria10_tse_sgmii_lvds_top.vhd
test_bench_files =
tb_ip_arria10_tse_sgmii_lvds_top.vhd
tb_ip_arria10_tse_sgmii_lvds.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
......
libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds_top.vhd deleted 100644 → 0
+ 0
− 134
View file @ 66cfd88c
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for generated ip_arria10_tse_sgmii_lvds.vhd
-- Description:
-- This wrapper avoids the need to vmap the ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library
-- in the tech_tse library that instantiate this IP.
-- Remarks:
-- . Manually created from generated ip_arria10_tse_sgmii_lvds.vhd.
library IEEE;
use IEEE.std_logic_1164.all;
library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140;
entity ip_arria10_tse_sgmii_lvds_top is
port (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
reset : in std_logic := '0'; -- reset_connection.reset
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
reg_rd : in std_logic := '0'; -- .read
reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
reg_wr : in std_logic := '0'; -- .write
reg_busy : out std_logic; -- .waitrequest
reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
ff_rx_eop : out std_logic; -- .endofpacket
rx_err : out std_logic_vector(5 downto 0); -- .error
ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
ff_rx_rdy : in std_logic := '0'; -- .ready
ff_rx_sop : out std_logic; -- .startofpacket
ff_rx_dval : out std_logic; -- .valid
ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
ff_tx_eop : in std_logic := '0'; -- .endofpacket
ff_tx_err : in std_logic := '0'; -- .error
ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
ff_tx_rdy : out std_logic; -- .ready
ff_tx_sop : in std_logic := '0'; -- .startofpacket
ff_tx_wren : in std_logic := '0'; -- .valid
ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
ff_tx_septy : out std_logic; -- .ff_tx_septy
tx_ff_uflow : out std_logic; -- .tx_ff_uflow
ff_tx_a_full : out std_logic; -- .ff_tx_a_full
ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
ff_rx_dsav : out std_logic; -- .ff_rx_dsav
ff_rx_a_full : out std_logic; -- .ff_rx_a_full
ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
led_crs : out std_logic; -- status_led_connection.crs
led_link : out std_logic; -- .link
led_col : out std_logic; -- .col
led_an : out std_logic; -- .an
led_char_err : out std_logic; -- .char_err
led_disp_err : out std_logic; -- .disp_err
rx_recovclkout : out std_logic; -- serdes_control_connection.export
ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
rxp : in std_logic := '0'; -- serial_connection.rxp_0
txp : out std_logic -- .txp_0
);
end ip_arria10_tse_sgmii_lvds_top;
architecture str of ip_arria10_tse_sgmii_lvds_top is
begin
u_ip_arria10_tse_sgmii_lvds : entity ip_arria10_tse_sgmii_lvds_altera_eth_tse_140.ip_arria10_tse_sgmii_lvds
port map (
clk => clk, -- control_port_clock_connection.clk
reset => reset, -- reset_connection.reset
reg_data_out => reg_data_out, -- control_port.readdata
reg_rd => reg_rd, -- .read
reg_data_in => reg_data_in, -- .writedata
reg_wr => reg_wr, -- .write
reg_busy => reg_busy, -- .waitrequest
reg_addr => reg_addr, -- .address
ff_rx_clk => ff_rx_clk, -- receive_clock_connection.clk
ff_tx_clk => ff_tx_clk, -- transmit_clock_connection.clk
ff_rx_data => ff_rx_data, -- receive.data
ff_rx_eop => ff_rx_eop, -- .endofpacket
rx_err => rx_err, -- .error
ff_rx_mod => ff_rx_mod, -- .empty
ff_rx_rdy => ff_rx_rdy, -- .ready
ff_rx_sop => ff_rx_sop, -- .startofpacket
ff_rx_dval => ff_rx_dval, -- .valid
ff_tx_data => ff_tx_data, -- transmit.data
ff_tx_eop => ff_tx_eop, -- .endofpacket
ff_tx_err => ff_tx_err, -- .error
ff_tx_mod => ff_tx_mod, -- .empty
ff_tx_rdy => ff_tx_rdy, -- .ready
ff_tx_sop => ff_tx_sop, -- .startofpacket
ff_tx_wren => ff_tx_wren, -- .valid
ff_tx_crc_fwd => ff_tx_crc_fwd, -- mac_misc_connection.ff_tx_crc_fwd
ff_tx_septy => ff_tx_septy, -- .ff_tx_septy
tx_ff_uflow => tx_ff_uflow, -- .tx_ff_uflow
ff_tx_a_full => ff_tx_a_full, -- .ff_tx_a_full
ff_tx_a_empty => ff_tx_a_empty, -- .ff_tx_a_empty
rx_err_stat => rx_err_stat, -- .rx_err_stat
rx_frm_type => rx_frm_type, -- .rx_frm_type
ff_rx_dsav => ff_rx_dsav, -- .ff_rx_dsav
ff_rx_a_full => ff_rx_a_full, -- .ff_rx_a_full
ff_rx_a_empty => ff_rx_a_empty, -- .ff_rx_a_empty
ref_clk => ref_clk, -- pcs_ref_clk_clock_connection.clk
rxp => rxp, -- serial_connection.rxp_0
txp => txp, -- .txp_0
led_crs => led_crs, -- status_led_connection.crs
led_link => led_link, -- .link
led_col => led_col, -- .col
led_an => led_an, -- .an
led_char_err => led_char_err, -- .char_err
led_disp_err => led_disp_err, -- .disp_err
rx_recovclkout => rx_recovclkout -- serdes_control_connection.export
);
end str;
libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds_top.vhd → libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
+ 5
− 5
View file @ 49b268ed
......@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
-- Purpose: Testbench for ip_arria10_tse_sgmii_lvds_top.
-- Purpose: Testbench for ip_arria10_tse_sgmii_lvds.
-- Description:
-- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is
-- generated by the MegaWizard provides an elaborate testbench. For
......@@ -38,11 +38,11 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
ENTITY tb_ip_arria10_tse_sgmii_lvds_top IS
END tb_ip_arria10_tse_sgmii_lvds_top;
ENTITY tb_ip_arria10_tse_sgmii_lvds IS
END tb_ip_arria10_tse_sgmii_lvds;
ARCHITECTURE tb OF tb_ip_arria10_tse_sgmii_lvds_top IS
ARCHITECTURE tb OF tb_ip_arria10_tse_sgmii_lvds IS
CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
......@@ -631,7 +631,7 @@ BEGIN
WAIT;
END PROCESS;
dut : ENTITY work.ip_arria10_tse_sgmii_lvds_top
dut : ENTITY work.ip_arria10_tse_sgmii_lvds
-- The ip_arria10_tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
-- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment