Fixed compatibility issues with latest GIT revision and OpenCL BSP

concerning jesd204b IP

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd

@@ -94,8 +94,9 @@ ARCHITECTURE str OF ta2_unb2b_jesd204b IS
   SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); 
   SIGNAL dp_latency_adapter_rx_src_in_arr  : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
 
-  SIGNAL jesd204b_rx_src_out_arr           : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
-  SIGNAL jesd204b_frame_clk                : STD_LOGIC;
+  SIGNAL jesd204b_rx_sosi_arr              : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_rx_clk                   : STD_LOGIC;
+  SIGNAL jesd204b_rx_rst                   : STD_LOGIC;
 
   SIGNAL i_jesd204b_sync_n_arr             : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
   SIGNAL jesd204b_serial_rx_arr            : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0) := (OTHERS => '0');
@@ -107,15 +108,16 @@ BEGIN
   u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
   GENERIC MAP(
     g_sim                => c_sim,                
-    g_nof_channels       => c_nof_streams_jesd204b    
+    g_nof_streams        => c_nof_streams_jesd204b    
   )
   PORT MAP(
     jesd204b_refclk      => jesd204b_refclk,   
     jesd204b_sysref      => jesd204b_sysref,   
     jesd204b_sync_n_arr  => i_jesd204b_sync_n_arr,   
   
-    rx_src_out_arr       => jesd204b_rx_src_out_arr,          
-    jesd204b_frame_clk   => jesd204b_frame_clk,          
+    rx_sosi_arr          => jesd204b_rx_sosi_arr,          
+    rx_clk               => jesd204b_rx_clk,
+    rx_rst               => jesd204b_rx_rst,         
   
     -- MM
     mm_clk               => mm_clk,           
@@ -134,10 +136,10 @@ BEGIN
     -- RX FIFO: adc_clk -> kernel_clk
     ---------------------------------------------------------------------------------------
 
-    dp_fifo_dc_rx_snk_in_arr(stream).data(13 DOWNTO 0) <= jesd204b_rx_src_out_arr(stream).data(15 DOWNTO 2);
-    dp_fifo_dc_rx_snk_in_arr(stream).data(14) <= jesd204b_rx_src_out_arr(stream).data(15);
-    dp_fifo_dc_rx_snk_in_arr(stream).data(15) <= jesd204b_rx_src_out_arr(stream).data(15);
-    dp_fifo_dc_rx_snk_in_arr(stream).valid <= dp_fifo_dc_rx_snk_out_arr(stream).ready AND jesd204b_rx_src_out_arr(stream).valid;
+    dp_fifo_dc_rx_snk_in_arr(stream).data(13 DOWNTO 0) <= jesd204b_rx_sosi_arr(stream).data(15 DOWNTO 2);
+    dp_fifo_dc_rx_snk_in_arr(stream).data(14) <= jesd204b_rx_sosi_arr(stream).data(15);
+    dp_fifo_dc_rx_snk_in_arr(stream).data(15) <= jesd204b_rx_sosi_arr(stream).data(15);
+    dp_fifo_dc_rx_snk_in_arr(stream).valid <= dp_fifo_dc_rx_snk_out_arr(stream).ready AND jesd204b_rx_sosi_arr(stream).valid;
 
     u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
     GENERIC MAP (
@@ -149,8 +151,8 @@ BEGIN
       g_fifo_size   => c_rx_fifo_size
     )
     PORT MAP (
-      wr_rst      => kernel_reset,
-      wr_clk      => jesd204b_frame_clk,
+      wr_rst      => jesd204b_rx_rst,
+      wr_clk      => jesd204b_rx_clk,
       rd_rst      => kernel_reset,
       rd_clk      => kernel_clk,
     

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd

@@ -857,7 +857,7 @@ BEGIN
       reg_fpga_voltage_sens_read_export         => reg_fpga_voltage_sens_mosi.rd,
       reg_fpga_voltage_sens_readdata_export     => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
 
-      rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
+      rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-4 DOWNTO 0), --temp fix
       rom_system_info_write_export              => rom_unb_system_info_mosi.wr,
       rom_system_info_writedata_export          => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
       rom_system_info_read_export               => rom_unb_system_info_mosi.rd,
@@ -869,7 +869,7 @@ BEGIN
       pio_system_info_read_export               => reg_unb_system_info_mosi.rd,
       pio_system_info_readdata_export           => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
 
-      pio_pps_address_export                    => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+      pio_pps_address_export                    => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-2 DOWNTO 0), -- temp fix
       pio_pps_write_export                      => reg_ppsh_mosi.wr,
       pio_pps_writedata_export                  => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
       pio_pps_read_export                       => reg_ppsh_mosi.rd,

libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg

@@ -2,7 +2,7 @@
 hdl_lib_name = ip_arria10_e1sg_jesd204b
 hdl_library_clause_name = ip_arria10_e1sg_jesd204b_lib
 hdl_lib_uses_synth = technology tech_pll common dp
-hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
+hdl_lib_uses_sim = #ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
 # hdl_lib_uses_sim =
 hdl_lib_technology = ip_arria10_e1sg