processed review comment

libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd

@@ -253,8 +253,8 @@ BEGIN
 
       -- No need to transfer eop counter across clock domains for single clock
       ELSE 
-        wr_eop_busy <= '0'; -- To prevent inferred latch.
-        wr_eop_new  <= '0'; -- To prevent inferred latch.
+        wr_eop_busy <= '0'; -- Not used here, fix value to prevent inferred latch.
+        wr_eop_new  <= '0'; -- Not used here, fix value to prevent inferred latch.
         IF snk_in.eop = '1' THEN
           wr_eop_cnt <= 1; -- wr_eop_cnt can simply be set to 1 instead of counting as it is immidiatly processed due to having a single clock.
         ELSE