Add g_block_size. Add in_en for stimuli.

libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd

@@ -47,7 +47,7 @@ use work.tb_dp_pkg.all;
 entity tb_dp_fifo_fill_eop is
   generic (
     -- Try FIFO settings
-    g_dut_use_dual_clock  : boolean := true;
+    g_dut_use_dual_clock  : boolean := false;
     g_dut_use_bsn         : boolean := false;
     g_dut_use_empty       : boolean := false;
     g_dut_use_channel     : boolean := false;
@@ -55,9 +55,10 @@ entity tb_dp_fifo_fill_eop is
     g_dut_fifo_rl         : natural := 1;  -- internal RL,  use 0 for look ahead FIFO, default 1 for normal FIFO
     g_dut_fifo_size       : natural := 128;
     g_dut_fifo_fill       : natural := 100;  -- selectable >= 0 for dp_fifo_fill
+    g_block_size          : natural := 14;  -- to verify g_block_size > or < g_dut_fifo_fill
     g_dut_use_rd_fill_32b : boolean := false;
-    g_dut_use_gap         : boolean := true;
-    g_dut_use_random_ctrl : boolean := true
+    g_dut_use_gap         : boolean := false;
+    g_dut_use_random_ctrl : boolean := false
   );
 end tb_dp_fifo_fill_eop;
 
@@ -75,7 +76,7 @@ architecture tb of tb_dp_fifo_fill_eop is
   constant c_tx_latency     : natural := c_dut_in_latency;  -- TX ready latency of TB
   constant c_tx_void        : natural := sel_a_b(c_tx_latency, 1, 0);  -- used to avoid empty range VHDL warnings when c_tx_latency=0
   constant c_tx_offset_sop  : natural := 3;
-  constant c_tx_period_sop  : natural := 14;  -- sop in data valid cycle 3,  17,  31, ...
+  constant c_tx_period_sop  : natural := g_block_size;  -- sop in data valid cycle 3,  17,  31, ...
   constant c_tx_offset_eop  : natural := sel_a_b(g_dut_use_gap, 12, 16);  -- eop in data valid cycle 12,  26,  40, ...
   constant c_tx_period_eop  : natural := c_tx_period_sop;
   constant c_tx_offset_sync : natural := 3;  -- sync in data valid cycle 3, 20, 37, ...
@@ -115,6 +116,7 @@ architecture tb of tb_dp_fifo_fill_eop is
   signal in_val         : std_logic;
   signal in_sop         : std_logic;
   signal in_eop         : std_logic;
+  signal in_en          : std_logic := '0';
 
   signal wr_ful         : std_logic;
   signal rd_usedw       : std_logic_vector(ceil_log2(largest(g_dut_fifo_size, g_dut_fifo_fill + c_dut_fifo_af_margin + 2)) - 1 downto 0);
@@ -148,8 +150,6 @@ architecture tb of tb_dp_fifo_fill_eop is
 
 begin
 
-
-
   clk <= not clk or tb_end after clk_period / 2;
   rst <= '1', '0' after clk_period * 7;
 
@@ -159,7 +159,6 @@ begin
   -- Input data
   cnt_val <= in_ready and cnt_en and not gap_en when g_dut_use_random_ctrl else in_ready and not gap_en;
 
-
   proc_dp_cnt_dat(rst, clk, cnt_val, cnt_dat);
   proc_dp_tx_data(c_tx_latency, rst, clk, cnt_val, cnt_dat, tx_data, tx_val, in_data, in_val);
   proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
@@ -169,6 +168,23 @@ begin
     proc_dp_tx_ctrl(c_tx_offset_gap, c_tx_period_gap, in_data, in_val, gap_en);
   end generate;
 
+  -- Use in_en to ensure that in_sosi starts with in_sop, so no spurious
+  -- in_eop or in_val without an in_sop. The FIFO will ignore these
+  -- spurious in_eop or in_val, but for testing the fill_eop mechanism
+  -- it is more clear to test with only complete input blocks. The
+  -- general assumption is that only complete blocks are allowed to enter
+  -- the application code, so incomplete blocks are already avoided at the
+  -- external interface code of the FPGA and by making sure that FIFOs
+  -- will stop accepting new blocks before they would overflow.
+  p_in_en : process
+  begin
+    wait until in_sop = '1';
+    wait until in_eop = '1';
+    wait until in_sop = '1';
+    in_en <= '1';
+    wait;
+  end process;
+
   in_bsn     <= INCR_UVEC(in_data, c_bsn_offset);
   in_empty   <= INCR_UVEC(in_data, c_empty_offset);
   in_channel <= INCR_UVEC(in_data, c_channel_offset);
@@ -236,10 +252,10 @@ begin
   in_sosi.bsn(c_dp_bsn_w - 1 downto 0)   <= in_bsn(c_dp_bsn_w - 1 downto 0);
   in_sosi.empty                        <= in_empty(c_dp_empty_w - 1 downto 0);
   in_sosi.channel                      <= in_channel(c_dp_channel_w - 1 downto 0);
-  in_sosi.sync                         <= in_sync;
-  in_sosi.valid                        <= (in_val and not gap_en);
-  in_sosi.sop                          <= in_sop;
-  in_sosi.eop                          <= in_eop;
+  in_sosi.sync                         <= in_en and in_sync;
+  in_sosi.valid                        <= in_en and (in_val and not gap_en);
+  in_sosi.sop                          <= in_en and in_sop;
+  in_sosi.eop                          <= in_en and in_eop;
 
   out_siso.ready <= out_ready;  -- SISO
   out_siso.xon   <= '1';

libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd

@@ -45,7 +45,19 @@ end tb_tb_dp_fifo_fill_eop;
 architecture tb of tb_tb_dp_fifo_fill_eop is
   signal tb_end : std_logic := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 begin
-  -- Try FIFO settings : GENERIC MAP (g_dut_use_dual_clock, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_fifo_rl, g_dut_fifo_size, g_dut_fifo_fill, g_dut_use_rd_fill_32b, g_dut_use_gap, g_dut_use_random_ctrl)
+  -- Try FIFO settings
+  -- g_dut_use_dual_clock  : boolean := true;
+  -- g_dut_use_bsn         : boolean := false;
+  -- g_dut_use_empty       : boolean := false;
+  -- g_dut_use_channel     : boolean := false;
+  -- g_dut_use_sync        : boolean := false;
+  -- g_dut_fifo_rl         : natural := 1;  -- internal RL,  use 0 for look ahead FIFO, default 1 for normal FIFO
+  -- g_dut_fifo_size       : natural := 128;
+  -- g_dut_fifo_fill       : natural := 100;  -- selectable >= 0 for dp_fifo_fill
+  -- g_block_size          : natural := 14;
+  -- g_dut_use_rd_fill_32b : boolean := false;
+  -- g_dut_use_gap         : boolean := true;
+  -- g_dut_use_random_ctrl : boolean := true
 
   u_dut_sc_1             : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => false, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => false);
   u_dut_sc_1_no_gap      : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => false, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => false, g_dut_use_gap => false);
@@ -59,4 +71,8 @@ begin
   u_dut_dc_1_rand_no_gap : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => true,  g_dut_fifo_rl => 1, g_dut_use_random_ctrl => true, g_dut_use_gap => false);
   u_dut_sc_0_rand_no_gap : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => false, g_dut_fifo_rl => 0, g_dut_use_random_ctrl => true, g_dut_use_gap => false);
   u_dut_dc_0_rand_no_gap : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => true,  g_dut_fifo_rl => 0, g_dut_use_random_ctrl => true, g_dut_use_gap => false);
+
+  u_dut_sc_1_blk_gt_fill : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => false, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => false, g_dut_use_gap => false,
+                                                                        g_dut_fifo_fill => 10, g_block_size => 20);
+
 end tb;