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Commit 4738bbf7 authored by Zanting's avatar Zanting
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Reverted to own pll/dll for 4g single rank slave

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boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+ 4
− 5
View file @ 4738bbf7
...@@ -2,7 +2,7 @@ hdl_lib_name = unb1_test_ddr_MB_I ...@@ -2,7 +2,7 @@ hdl_lib_name = unb1_test_ddr_MB_I
hdl_library_clause_name = unb1_test_ddr_MB_I_lib hdl_library_clause_name = unb1_test_ddr_MB_I_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
...@@ -34,10 +34,9 @@ quartus_tcl_files = ...@@ -34,10 +34,9 @@ quartus_tcl_files =
quartus_vhdl_files = quartus_vhdl_files =
quartus_qip_files = quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
#$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+ 4
− 5
View file @ 4738bbf7
...@@ -2,7 +2,7 @@ hdl_lib_name = unb1_test_ddr_MB_II ...@@ -2,7 +2,7 @@ hdl_lib_name = unb1_test_ddr_MB_II
hdl_library_clause_name = unb1_test_ddr_MB_II_lib hdl_library_clause_name = unb1_test_ddr_MB_II_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave hdl_lib_excludes = ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
...@@ -34,10 +34,9 @@ quartus_tcl_files = ...@@ -34,10 +34,9 @@ quartus_tcl_files =
quartus_vhdl_files = quartus_vhdl_files =
quartus_qip_files = quartus_qip_files =
$HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
#$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+ 1
− 1
View file @ 4738bbf7
...@@ -2,7 +2,7 @@ hdl_lib_name = unb1_test_ddr_MB_I_II ...@@ -2,7 +2,7 @@ hdl_lib_name = unb1_test_ddr_MB_I_II
hdl_library_clause_name = unb1_test_ddr_MB_I_II_lib hdl_library_clause_name = unb1_test_ddr_MB_I_II_lib
hdl_lib_uses_synth = unb1_board unb1_test hdl_lib_uses_synth = unb1_board unb1_test
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave ip_stratixiv_ddr3_uphy_16g_dual_rank_800 ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
......
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