added ip_arria10_e1sg_complex_mult

libraries/technology/mult/hdllib.cfg

@@ -5,6 +5,7 @@ hdl_lib_uses_synth = common technology
                      ip_arria10_mult
                      ip_arria10_complex_mult
                      ip_arria10_complex_mult_rtl
+                     ip_arria10_e1sg_complex_mult
                      ip_arria10_e3sge3_mult_add4
                      ip_arria10_e1sg_mult_add4
 hdl_lib_uses_sim = 
@@ -14,6 +15,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_mult                  ip_arria10_mult_lib
     ip_arria10_complex_mult          ip_arria10_complex_mult_altmult_complex_150
     ip_arria10_complex_mult_rtl      ip_arria10_complex_mult_rtl_lib
+    ip_arria10_e1sg_complex_mult     ip_arria10_e1sg_complex_mult_altmult_complex_170
     ip_arria10_e3sge3_mult_add4      ip_arria10_e3sge3_mult_add4_lib
     ip_arria10_e1sg_mult_add4        ip_arria10_e1sg_mult_add4_lib
 

libraries/technology/mult/tech_complex_mult.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_stratixiv_mult_lib;
 --LIBRARY ip_arria10_mult_lib;
 --LIBRARY ip_arria10_mult_rtl_lib;
 LIBRARY ip_arria10_complex_mult_altmult_complex_150;
+LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
 LIBRARY ip_arria10_complex_mult_rtl_lib;
 
 
@@ -164,8 +165,9 @@ begin
     result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
 
   END GENERATE;
-
-  gen_ip_arria10_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10 AND g_variant="RTL") GENERATE
+  -- RTL variant is the same for unb2, unb2a and unb2b
+  gen_ip_arria10_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND 
+      ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg ) AND g_variant="RTL") GENERATE
     u0 : ip_arria10_complex_mult_rtl
   GENERIC MAP(
     g_in_a_w           => g_in_a_w,
@@ -190,6 +192,35 @@ begin
     );
   END GENERATE;
 
+
+  gen_ip_arria10_e1sg_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10_e1sg AND g_variant="IP") GENERATE
+
+    -- Adapt DSP input widths
+    ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
+    ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
+    br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
+    bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
+
+
+    u0 : ip_arria10_e1sg_complex_mult
+    PORT MAP (
+         aclr        => rst,
+         clock       => clk,
+         dataa_imag  => ai,
+         dataa_real  => ar,
+         datab_imag  => bi,
+         datab_real  => br,
+         ena         => clken,
+         result_imag => mult_im,
+         result_real => mult_re
+         );
+
+    -- Back to true input widths and then resize for output width
+    result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+    result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+
+  END GENERATE;
+
   -------------------------------------------------------------------------------
   -- Model: forward concatenated inputs to the 'result' output
   --