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Commit 44886691 authored by Eric Kooistra's avatar Eric Kooistra
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Use tech_mac_10g and tr_xaui from /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk for StratixIV

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...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, diag_lib, tr_xaui_lib, technology_lib, tech_memory_lib, tech_transceiver_lib; LIBRARY IEEE, common_lib, dp_lib, diag_lib, tr_xaui_lib, technology_lib, tech_mac_10g_lib;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
...@@ -269,88 +269,6 @@ ARCHITECTURE str OF tr_10GbE IS ...@@ -269,88 +269,6 @@ ARCHITECTURE str OF tr_10GbE IS
); );
end component; end component;
component mac_10g is
port (
csr_clk_clk : in std_logic;
csr_reset_reset_n : in std_logic;
csr_address : in std_logic_vector(12 downto 0);
csr_waitrequest : out std_logic;
csr_read : in std_logic;
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic;
csr_writedata : in std_logic_vector(31 downto 0);
tx_clk_clk : in std_logic;
tx_reset_reset_n : in std_logic;
avalon_st_tx_startofpacket : in std_logic;
avalon_st_tx_valid : in std_logic;
avalon_st_tx_data : in std_logic_vector(63 downto 0);
avalon_st_tx_empty : in std_logic_vector(2 downto 0);
avalon_st_tx_ready : out std_logic;
avalon_st_tx_error : in std_logic_vector(0 downto 0);
avalon_st_tx_endofpacket: in std_logic;
avalon_st_pause_data : in std_logic_vector(1 downto 0);
xgmii_tx_data : out std_logic_vector(71 downto 0);
avalon_st_txstatus_valid: out std_logic;
avalon_st_txstatus_data : out std_logic_vector(39 downto 0);
avalon_st_txstatus_error: out std_logic_vector(6 downto 0);
rx_clk_clk : in std_logic;
rx_reset_reset_n : in std_logic;
xgmii_rx_data : in std_logic_vector(71 downto 0);
avalon_st_rx_startofpacket : out std_logic;
avalon_st_rx_endofpacket: out std_logic;
avalon_st_rx_valid : out std_logic;
avalon_st_rx_ready : in std_logic;
avalon_st_rx_data : out std_logic_vector(63 downto 0);
avalon_st_rx_empty : out std_logic_vector(2 downto 0);
avalon_st_rx_error : out std_logic_vector(5 downto 0);
avalon_st_rxstatus_valid: out std_logic;
avalon_st_rxstatus_data : out std_logic_vector(39 downto 0);
avalon_st_rxstatus_error: out std_logic_vector(6 downto 0);
link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0)
);
end component mac_10g;
component tr_xaui is
generic (
g_technology : NATURAL := c_tech_select_default;
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
g_use_xgmii : BOOLEAN := FALSE; -- Don't use streaming I/O but XGMII (e.g. conenct to 10GbE MAC)
g_nof_xaui : NATURAL := 1; -- Up to 3 (hard XAUI only) supported
g_mdio : BOOLEAN := FALSE;
g_mdio_epcs_dis : BOOLEAN := FALSE -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
);
port (
tr_clk : IN STD_LOGIC;
cal_rec_clk : IN STD_LOGIC;
mm_clk : IN STD_LOGIC := '0';
mm_rst : IN STD_LOGIC := '0';
rx_clk : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
rx_rst : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
-- rx_sosi_arr : OUT t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
-- rx_siso_arr : IN t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
tx_clk : IN STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
tx_rst : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
-- tx_sosi_arr : IN t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
-- tx_siso_arr : OUT t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
xaui_rx : IN t_xaui_arr(g_nof_macs-1 DOWNTO 0);
xaui_tx : OUT t_xaui_arr(g_nof_macs-1 DOWNTO 0);
xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst;
xaui_miso : OUT t_mem_miso;
mdio_mosi_arr : IN t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
mdio_miso_arr : OUT t_mem_miso_arr(g_nof_macs-1 DOWNTO 0);
mdio_rst : OUT STD_LOGIC;
mdio_mdc : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
mdio_mdat_in : IN STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
mdio_mdat_oen : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0)
);
end component;
BEGIN BEGIN
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -570,55 +488,32 @@ BEGIN ...@@ -570,55 +488,32 @@ BEGIN
gen_ip_stratixiv : if g_technology=c_tech_stratixiv generate gen_ip_stratixiv : if g_technology=c_tech_stratixiv generate
gen_mac_10g : FOR i IN 0 TO sel_a_b(g_lpbk_sosi, 0, g_nof_macs)-1 GENERATE gen_mac_10g : FOR i IN 0 TO sel_a_b(g_lpbk_sosi, 0, g_nof_macs)-1 GENERATE
mac_10g_snk_out_arr(i).xon <= tx_rst_n_arr(i); u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
GENERIC MAP (
u_mac_10g : mac_10g g_technology => g_technology,
g_pre_header_padding => FALSE
)
PORT MAP ( PORT MAP (
csr_clk_clk => mm_clk, -- MM
csr_reset_reset_n => mm_rst_n, mm_clk => mm_clk,
csr_address => reg_mac_mosi_arr(i).address(c_mac_mm_addr_w-1 DOWNTO 0), mm_rst => mm_rst,
csr_waitrequest => reg_mac_miso_arr(i).waitrequest, csr_mosi => reg_mac_mosi_arr(i), -- CSR = control status register
csr_read => reg_mac_mosi_arr(i).rd, csr_miso => reg_mac_miso_arr(i),
csr_readdata => reg_mac_miso_arr(i).rddata(c_word_w-1 DOWNTO 0),
csr_write => reg_mac_mosi_arr(i).wr, -- ST
csr_writedata => reg_mac_mosi_arr(i).wrdata(c_word_w-1 DOWNTO 0), tx_clk => tx_clk_arr(i), -- 156.25 MHz local reference
tx_rst => tx_rst_arr(i),
tx_clk_clk => tx_clk_arr(i), tx_snk_in => mac_10g_snk_in_arr(i), -- 64 bit data
tx_reset_reset_n => tx_rst_n_arr(i), tx_snk_out => mac_10g_snk_out_arr(i),
avalon_st_tx_startofpacket => mac_10g_snk_in_arr(i).sop, rx_clk => rx_clk_arr(i), -- 156.25 MHz from rx phy
avalon_st_tx_valid => mac_10g_snk_in_arr(i).valid, rx_rst => rx_rst_arr(i),
avalon_st_tx_data => mac_10g_snk_in_arr(i).data(c_xgmii_data_w-1 DOWNTO 0), rx_src_out => mac_10g_src_out_arr(i), -- 64 bit data
avalon_st_tx_empty => mac_10g_snk_in_arr(i).empty(2 DOWNTO 0), rx_src_in => mac_10g_src_in_arr(i),
avalon_st_tx_ready => mac_10g_snk_out_arr(i).ready,
avalon_st_tx_error => mac_10g_snk_in_arr(i).err(0 DOWNTO 0), -- XGMII
avalon_st_tx_endofpacket => mac_10g_snk_in_arr(i).eop, xgmii_tx_data => mac_xgmii_tx_dc_arr(i), -- 72 bit
avalon_st_pause_data => (OTHERS=>'0'), xgmii_rx_data => mac_xgmii_rx_dc_arr(i) -- 72 bit
xgmii_tx_data => mac_xgmii_tx_dc_arr(i),
avalon_st_txstatus_valid => OPEN,
avalon_st_txstatus_data => OPEN,
avalon_st_txstatus_error => OPEN,
rx_clk_clk => rx_clk_arr(i),
rx_reset_reset_n => rx_rst_n_arr(i),
xgmii_rx_data => mac_xgmii_rx_dc_arr(i),
avalon_st_rx_startofpacket => mac_10g_src_out_arr(i).sop,
avalon_st_rx_endofpacket => mac_10g_src_out_arr(i).eop,
avalon_st_rx_valid => mac_10g_src_out_arr(i).valid,
avalon_st_rx_ready => mac_10g_src_in_arr(i).ready,
avalon_st_rx_data => mac_10g_src_out_arr(i).data(c_xgmii_data_w-1 DOWNTO 0),
avalon_st_rx_empty => mac_10g_src_out_arr(i).empty(2 DOWNTO 0),
avalon_st_rx_error => mac_10g_src_out_arr(i).err(5 DOWNTO 0),
avalon_st_rxstatus_valid => OPEN,
avalon_st_rxstatus_data => OPEN,
avalon_st_rxstatus_error => OPEN,
link_fault_status_xgmii_rx_data => OPEN
); );
END GENERATE; END GENERATE;
...@@ -640,54 +535,59 @@ BEGIN ...@@ -640,54 +535,59 @@ BEGIN
mac_xgmii_rx_dc_arr <= xaui_xgmii_rx_dc_arr; mac_xgmii_rx_dc_arr <= xaui_xgmii_rx_dc_arr;
END GENERATE; END GENERATE;
--------------------------------------------------------------------------------------- u_tr_xaui : ENTITY tr_xaui_lib.tr_xaui
-- tr_xaui
---------------------------------------------------------------------------------------
u_tr_xaui: tr_xaui
GENERIC MAP ( GENERIC MAP (
g_technology => g_technology,
g_sim => g_sim, g_sim => g_sim,
g_sim_level => g_sim_level, g_sim_level => g_sim_level,
g_use_xgmii => TRUE, -- Use XGMII direct g_use_xgmii => TRUE, -- Use XGMII direct
g_nof_xaui => g_nof_macs,
g_mdio => g_use_mdio, g_mdio => g_use_mdio,
g_mdio_epcs_dis => g_mdio_epcs_dis, g_mdio_epcs_dis => g_mdio_epcs_dis
g_nof_xaui => g_nof_macs
) )
PORT MAP ( PORT MAP (
-- Transceiver PLL reference clock
tr_clk => tr_clk, tr_clk => tr_clk,
mm_rst => mm_rst, -- Calibration & reconfig clock
cal_rec_clk => cal_rec_clk,
-- MM clock for register of optional MDIO master
mm_clk => mm_clk, mm_clk => mm_clk,
mm_rst => mm_rst,
-- Serial data -- Streaming RX interfaces
xaui_tx => xaui_tx_arr, rx_clk => rx_clk_arr,
xaui_rx => xaui_rx_arr, rx_rst => rx_rst_arr,
-- Streaming TX interfaces
tx_clk => tx_clk_arr,
tx_rst => tx_rst_arr,
-- XGMII direct -- Direct XGMII interface
xgmii_tx_dc_arr => xaui_xgmii_tx_dc_arr, xgmii_tx_dc_arr => xaui_xgmii_tx_dc_arr,
xgmii_rx_dc_arr => xaui_xgmii_rx_dc_arr, xgmii_rx_dc_arr => xaui_xgmii_rx_dc_arr,
-- MDIO --Serial I/O
mdio_rst => mdio_rst, xaui_rx => xaui_rx_arr,
mdio_mdc => mdio_mdc_arr, xaui_tx => xaui_tx_arr,
mdio_mdat_in => mdio_mdat_in_arr,
mdio_mdat_oen => mdio_mdat_oen_arr, -- XAUI PHY IP MM control/status
xaui_mosi => xaui_mosi,
xaui_miso => xaui_miso,
-- MDIO master = mm slave
mdio_mosi_arr => mdio_mosi_arr(g_nof_macs-1 DOWNTO 0), mdio_mosi_arr => mdio_mosi_arr(g_nof_macs-1 DOWNTO 0),
mdio_miso_arr => mdio_miso_arr(g_nof_macs-1 DOWNTO 0), mdio_miso_arr => mdio_miso_arr(g_nof_macs-1 DOWNTO 0),
-- XGMII I/O -- MDIO External clock and serial data.
rx_rst => rx_rst_arr, mdio_rst => mdio_rst,
rx_clk => rx_clk_arr, mdio_mdc => mdio_mdc_arr,
mdio_mdat_in => mdio_mdat_in_arr,
tx_rst => tx_rst_arr, mdio_mdat_oen => mdio_mdat_oen_arr
tx_clk => tx_clk_arr,
cal_rec_clk => cal_rec_clk,
xaui_mosi => xaui_mosi,
xaui_miso => xaui_miso
); );
end generate; END GENERATE;
---------------------- Arria 10 ------------------------- ---------------------- Arria 10 -------------------------
......
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