Initial commit of dp_selector_arr and dp_selector

libraries/base/dp/hdllib.cfg

@@ -160,6 +160,8 @@ synth_files =
     src/vhdl/dp_block_reshape_sync.vhd
     src/vhdl/dp_complex_mult.vhd
     src/vhdl/dp_complex_add.vhd
+    src/vhdl/dp_selector_arr.vhd
+    src/vhdl/dp_selector.vhd
     tb/vhdl/dp_stream_player.vhd
     tb/vhdl/dp_sosi_recorder.vhd
     tb/vhdl/dp_stream_rec_play.vhd

libraries/base/dp/src/vhdl/dp_selector.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Single instance wrapper for dp_selector_arr.
+-- Description:
+-- Remark:
+-- . See dp_selector_arr.vhd for more detail.
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+LIBRARY common_lib, common_mult_lib;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_selector IS
+  GENERIC (
+    g_pipeline    : NATURAL := 1
+  );
+  PORT (
+    mm_rst                  : IN  STD_LOGIC;
+    mm_clk                  : IN  STD_LOGIC;
+    dp_rst                  : IN  STD_LOGIC := '0';
+    dp_clk                  : IN  STD_LOGIC;
+
+    -- MM interface
+    reg_selector_mosi       : IN  t_mem_mosi := c_mem_mosi_rst; 
+    reg_selector_miso       : OUT t_mem_miso;
+
+    pipe_sosi               : IN  t_dp_sosi;
+    ref_sosi                : IN  t_dp_sosi;
+    out_sosi                : OUT t_dp_sosi
+  );
+END dp_selector;
+
+ARCHITECTURE str OF dp_selector IS
+
+BEGIN
+
+  u_dp_selector_arr : ENTITY work.dp_selector_arr
+  GENERIC MAP (
+    g_nof_arr   => 1,
+    g_pipeline  => g_pipeline
+  )
+  PORT MAP (
+    mm_rst             => mm_rst,
+    mm_clk             => mm_clk,
+    dp_rst             => dp_rst,
+    dp_clk             => dp_clk,
+
+    reg_selector_mosi  => reg_selector_mosi,
+    reg_selector_miso  => reg_selector_miso,
+
+    pipe_sosi_arr(0)   =>  pipe_sosi,  
+    ref_sosi_arr(0)    =>  ref_sosi,
+    out_sosi_arr(0)    =>  out_sosi
+  );
+
+END str;

libraries/base/dp/src/vhdl/dp_selector_arr.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Selects between two input arrays using MM interface.
+-- Description:
+-- . Output is set to pipe_sosi_arr when register is set to '1', output is set 
+-- . to ref_sosi_arr when register is set to '0'. pipe_sosi_arr input can be
+-- . pipelined, this is configured with the generic "g_pipeline".
+-- Remark:
+-- . The select register is synchronised with the sync signal in ref_sosi_arr.
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+LIBRARY common_lib, common_mult_lib;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_selector_arr IS
+  GENERIC (
+    g_nof_arr     : NATURAL := 1;
+    g_pipeline    : NATURAL := 1
+  );
+  PORT (
+    mm_rst                  : IN  STD_LOGIC;
+    mm_clk                  : IN  STD_LOGIC;
+    dp_rst                  : IN  STD_LOGIC := '0';
+    dp_clk                  : IN  STD_LOGIC;
+
+    -- MM interface
+    reg_selector_mosi       : IN  t_mem_mosi := c_mem_mosi_rst; 
+    reg_selector_miso       : OUT t_mem_miso;
+
+    pipe_sosi_arr           : IN  t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0);
+    ref_sosi_arr            : IN  t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0);
+    out_sosi_arr            : OUT t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0)
+  );
+END dp_selector_arr;
+
+ARCHITECTURE str OF dp_selector_arr IS
+
+  SIGNAL reg_selector_en : STD_LOGIC_VECTOR(c_mem_reg.dat_w*c_mem_reg.nof_dat-1 DOWNTO 0);
+  SIGNAL n_en            : STD_LOGIC;
+  SIGNAL switch_select   : STD_LOGIC;
+
+  SIGNAL pipelined_pipe_sosi_arr  : t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0);
+  SIGNAL select_sosi_arr          : t_dp_sosi_arr(g_nof_arr-1 DOWNTO 0);
+
+BEGIN
+
+  u_mms_common_reg : ENTITY common_lib.mms_common_reg
+  GENERIC MAP (
+    g_mm_reg       => c_mem_reg
+  )
+  PORT MAP (
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+    st_rst         => dp_rst,
+    st_clk         => dp_clk,
+
+    reg_mosi       => reg_selector_mosi,
+    reg_miso       => reg_selector_miso,
+
+    in_reg         => reg_selector_en,
+    out_reg        => reg_selector_en   
+  );
+
+
+  n_en <= NOT reg_selector_en(0);
+
+  u_common_switch : ENTITY common_lib.common_switch
+    PORT MAP (
+      rst         => dp_rst,  
+      clk         => dp_clk,
+      clken       => ref_sosi_arr(0).sync,
+      switch_high => reg_selector_en(0),
+      switch_low  => n_en,
+      out_level   => switch_select
+  );
+
+
+  u_pipeline_arr : ENTITY work.dp_pipeline_arr
+  GENERIC MAP (
+    g_nof_streams => g_nof_arr,
+    g_pipeline    => g_pipeline 
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    snk_in_arr   => pipe_sosi_arr,
+    src_out_arr  => pipelined_pipe_sosi_arr
+  );
+
+
+  select_sosi_arr <= pipelined_pipe_sosi_arr WHEN switch_select = '1' ELSE ref_sosi_arr;
+
+  u_pipeline_arr_out : ENTITY work.dp_pipeline_arr
+  GENERIC MAP (
+    g_nof_streams => g_nof_arr,
+    g_pipeline    => 1 
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    snk_in_arr   => select_sosi_arr,
+    src_out_arr  => out_sosi_arr
+  );
+
+END str;