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Commit 428bf5d7 authored by Zanting's avatar Zanting
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Updated DDR3 slave IP

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libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+ 0
− 7
View file @ 428bf5d7
......@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
......@@ -16,9 +13,5 @@ synth_files =
test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
quartus_qip_files =
generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.qip
libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+ 96
− 92
View file @ 428bf5d7
......@@ -2,16 +2,16 @@
// GENERATION: XML
// ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
// Generated using ACDS version 11.1sp2 259 at 2015.08.12.15:00:22
// Generated using ACDS version 11.1sp2 259 at 2015.09.01.15:07:56
`timescale 1 ps / 1 ps
module ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
input wire afi_clk, // afi_clk_in.clk
input wire afi_half_clk, // afi_half_clk_in.clk
input wire afi_reset_n, // afi_reset_in.reset_n
output wire [15:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [1:0] mem_ck, // .mem_ck
......@@ -40,25 +40,27 @@ module ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave (
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire [13:0] seriesterminationcontrol, // oct_sharing.seriesterminationcontrol
input wire [13:0] parallelterminationcontrol, // .parallelterminationcontrol
output wire pll_mem_clk, // pll_sharing.pll_mem_clk
output wire pll_write_clk, // .pll_write_clk
output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
output wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
output wire pll_locked, // .pll_locked
output wire pll_avl_clk, // .pll_avl_clk
output wire pll_config_clk, // .pll_config_clk
output wire [5:0] dll_delayctrl // dll_sharing.dll_delayctrl
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire [13:0] seriesterminationcontrol, // oct_sharing.seriesterminationcontrol
output wire [13:0] parallelterminationcontrol, // .parallelterminationcontrol
input wire pll_mem_clk, // pll_sharing.pll_mem_clk
input wire pll_write_clk, // .pll_write_clk
input wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
input wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
input wire pll_locked, // .pll_locked
input wire pll_avl_clk, // .pll_avl_clk
input wire pll_config_clk, // .pll_config_clk
input wire [5:0] dll_delayctrl // dll_sharing.dll_delayctrl
);
ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_0002 ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_inst (
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk_in.clk
.afi_half_clk (afi_half_clk), // afi_half_clk_in.clk
.afi_reset_n (afi_reset_n), // afi_reset_in.reset_n
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
......@@ -87,6 +89,8 @@ module ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave (
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.seriesterminationcontrol (seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (parallelterminationcontrol), // .parallelterminationcontrol
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
......@@ -317,9 +321,9 @@ endmodule
// Retrieval info: <generic name="HHP_REMAP_ADDR" value="true" />
// Retrieval info: <generic name="USE_SEQUENCER_APB_BRIDGE" value="false" />
// Retrieval info: <generic name="DEFAULT_FAST_SIM_MODEL" value="true" />
// Retrieval info: <generic name="PLL_SHARING_MODE" value="Master" />
// Retrieval info: <generic name="DLL_SHARING_MODE" value="Master" />
// Retrieval info: <generic name="OCT_SHARING_MODE" value="Slave" />
// Retrieval info: <generic name="PLL_SHARING_MODE" value="Slave" />
// Retrieval info: <generic name="DLL_SHARING_MODE" value="Slave" />
// Retrieval info: <generic name="OCT_SHARING_MODE" value="Master" />
// Retrieval info: <generic name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
// Retrieval info: <generic name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
// Retrieval info: <generic name="USE_FAKE_PHY" value="false" />
......
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