Added comments.

libraries/dsp/fft/src/vhdl/fft_switch.vhd

@@ -38,13 +38,12 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY fft_switch IS
   GENERIC (
-    g_nof_clk_per_sync : NATURAL := 200*10**6;
     g_fft_sz_w  : NATURAL;
     g_dat_w     : NATURAL
   );
   PORT (
-    in_re             : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-    in_im             : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    in_re       : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);  -- real input A
+    in_im       : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);  -- real input B
     in_val      : IN  STD_LOGIC;
     switch_en   : IN  STD_LOGIC := '1';
     out_re      : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
@@ -60,14 +59,13 @@ ARCHITECTURE rtl OF fft_switch IS
 
   CONSTANT c_nof_clk_per_block  : NATURAL := 2**g_fft_sz_w;
 
-  SIGNAL cnt           : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0);
+  SIGNAL cnt           : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0) := (OTHERS => '0');
   SIGNAL nxt_cnt       : STD_LOGIC_VECTOR(cnt'RANGE);
 
   SIGNAL lfsr_bit1     : STD_LOGIC;
   SIGNAL lfsr_bit2     : STD_LOGIC;
   SIGNAL lfsr_en       : STD_LOGIC;
 
-  SIGNAL nxt_out_val   : STD_LOGIC;
   SIGNAL nxt_out_re    : STD_LOGIC_VECTOR(in_re'RANGE);
   SIGNAL nxt_out_im    : STD_LOGIC_VECTOR(in_im'RANGE);
 
@@ -112,10 +110,10 @@ BEGIN
 
     IF switch_en = '1' THEN
       IF lfsr_bit1 = cnt(cnt'HIGH) THEN
-        nxt_out_re <= NEGATE_SVEC(in_re);
+        nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);  -- negate block of input A samples
       END IF;
       IF lfsr_bit2 = cnt(cnt'HIGH) THEN
-        nxt_out_im <= NEGATE_SVEC(in_im);
+        nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);  -- negate block of input B samples
       END IF;
     END IF;
   END PROCESS;

libraries/dsp/fft/src/vhdl/fft_unswitch.vhd

@@ -33,7 +33,6 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY fft_unswitch IS
   GENERIC (
-    g_nof_clk_per_sync : NATURAL := 200*10**6;
     g_fft_sz_w  : NATURAL;
     g_dat_w     : NATURAL
   );
@@ -56,7 +55,7 @@ ARCHITECTURE rtl OF fft_unswitch IS
 
   SIGNAL in_sosi       : t_dp_sosi;
 
-  SIGNAL cnt           : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0);
+  SIGNAL cnt           : STD_LOGIC_VECTOR(g_fft_sz_w DOWNTO 0) := (OTHERS => '0');
   SIGNAL nxt_cnt       : STD_LOGIC_VECTOR(cnt'RANGE);
 
   SIGNAL lfsr_bit1     : STD_LOGIC;
@@ -64,7 +63,6 @@ ARCHITECTURE rtl OF fft_unswitch IS
 
   SIGNAL lfsr_en       : STD_LOGIC;
 
-  SIGNAL nxt_out_val   : STD_LOGIC;
   SIGNAL nxt_out_re    : STD_LOGIC_VECTOR(in_re'RANGE);
   SIGNAL nxt_out_im    : STD_LOGIC_VECTOR(in_im'RANGE);
 
@@ -108,10 +106,17 @@ BEGIN
     nxt_out_im  <= in_im;
 
     IF switch_en = '1' THEN
-      IF (cnt(0) = '0' AND cnt(cnt'HIGH) = lfsr_bit1) OR
-         (cnt(0) = '1' AND cnt(cnt'HIGH) = lfsr_bit2) THEN
-        nxt_out_re <= NEGATE_SVEC(in_re);
-        nxt_out_im <= NEGATE_SVEC(in_im);
+      -- multiplexed spectrum for input A at index 0, B at index 1
+      IF cnt(0) = '0' THEN
+        IF cnt(cnt'HIGH) = lfsr_bit1 THEN  -- negate spectrum to undo negate of block of real input A
+          nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);
+          nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);
+        END IF;
+      ELSE
+        IF cnt(cnt'HIGH) = lfsr_bit2 THEN  -- negate spectrum to undo negate of block of real input B
+          nxt_out_re <= NEGATE_SVEC(in_re, g_dat_w);
+          nxt_out_im <= NEGATE_SVEC(in_im, g_dat_w);
+        END IF;
       END IF;
     END IF;
   END PROCESS;

libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd

@@ -97,14 +97,14 @@ ARCHITECTURE tb OF tb_fft_switch IS
   SIGNAL prev2_switch_b    : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
 
   SIGNAL mux_toggle        : STD_LOGIC := '0';
-  SIGNAL mux_re            : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
-  SIGNAL mux_im            : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
-  SIGNAL mux_val           : STD_LOGIC;
+  SIGNAL mux_re            : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL mux_im            : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL mux_val           : STD_LOGIC := '0';
 
   SIGNAL unswitch_en       : STD_LOGIC := '1';
   SIGNAL unswitch_re       : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
   SIGNAL unswitch_im       : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
-  SIGNAL unswitch_val      : STD_LOGIC;
+  SIGNAL unswitch_val      : STD_LOGIC := '0';
   SIGNAL prev1_unswitch_re : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
   SIGNAL prev1_unswitch_im : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
   SIGNAL prev2_unswitch_re : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
@@ -150,7 +150,7 @@ BEGIN
         END LOOP;
       END LOOP;
     END LOOP;
-    proc_common_wait_some_cycles(clk, g_nof_clk_per_sync*2);
+    proc_common_wait_some_cycles(clk, g_nof_clk_per_sync*g_nof_sync);
     tb_end <= '1';
     WAIT;
   END PROCESS;
@@ -185,7 +185,6 @@ BEGIN
 
   u_fft_switch : ENTITY work.fft_switch
   GENERIC MAP (
-    g_nof_clk_per_sync => g_nof_clk_per_sync,
     g_fft_sz_w => g_fft_size_w,
     g_dat_w    => c_dat_w
   )