added description and warning for reg_wr_arr.

libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd

@@ -44,6 +44,12 @@
 --   In fact g_readback could better be called g_st_readback. An alternative
 --   g_mm_readback could define direct read back in the MM clock domain and
 --   would allow leaving the in_reg not connected.
+-- . reg_wr_arr
+--   Provides write access pulse in dp_clk domain. However the pulse may arrive
+--   before the out_reg data, due to that the pulse and data do not cross the
+--   clock domain in the same way. A solution would be to use a single
+--   common_reg_cross_domain instance to transfer both the wr access info and
+--   the data.
 
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;