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Commit 41ffb62e authored by Job van Wee's avatar Job van Wee
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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+ 2
− 1
View file @ 41ffb62e
......@@ -62,7 +62,7 @@ END ddrctrl;
ARCHITECTURE str OF ddrctrl IS
-- constant for readability
CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data with for ddrctrl_repack
CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- the input data with for ddrctrl_repack
-- signals for connecting the components
......@@ -94,6 +94,7 @@ BEGIN
)
PORT MAP(
clk => clk,
rst => rst,
in_data => data, -- input data
out_of => out_of, -- amount of internal overflow
out_sosi => sosi -- output data
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_repack.vhd
+ 65
− 19
View file @ 41ffb62e
......@@ -41,6 +41,7 @@ ENTITY ddrctrl_repack IS
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_data : IN STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0); -- input data
out_of : OUT NATURAL := 0; -- amount of internal overflow this output
out_sosi : OUT t_dp_sosi := c_dp_sosi_init -- output data
......@@ -50,6 +51,8 @@ END ddrctrl_repack;
ARCHITECTURE rtl OF ddrctrl_repack IS
TYPE t_state IS (OVER_FLOW, FIRST_HALF, SECOND_HALF, RESET);
-- constant for readability
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152
......@@ -63,34 +66,77 @@ BEGIN
VARIABLE c_v : STD_LOGIC_VECTOR (k_c_v_w-1 DOWNTO 0) := (OTHERS => '0'); -- the vector that stores the input data until the data is put into the output data vector
VARIABLE c_v_count : NATURAL := 0; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
VARIABLE out_data_count : NATURAL := 0; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
VARIABLE state : t_state := FIRST_HALF; -- the state the process is currently in;
BEGIN
IF rising_edge(clk) THEN
IF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) THEN -- if the input data exceeds the output data vector width
IF (out_data_count = 1) THEN -- if the input data exceeds c_v widt
a_of := a_of + (g_in_data_w*(c_v_count+1)) - (c_out_data_w*(out_data_count+1)); -- check how much overflow there is and safe it in a_of
out_of <= a_of; -- set the output overflow to the overflow that maches the out_sosi.data vector
c_v(k_c_v_w - 1 DOWNTO k_c_v_w-(g_in_data_w - a_of)) := in_data(g_in_data_w - a_of - 1 DOWNTO 0); -- fill the rest of c_v untill the end
c_v(a_of - 1 DOWNTO 0) := in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_of); -- fill the start of c_v untill the a_of
out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
out_sosi.valid <= '1'; -- out_sosi.valid 1
c_v_count := 0; -- reset counter
out_data_count := 0; -- reset counter
Else -- if the input data exceeds output data vector width but not the c_v vector widt
CASE state IS
WHEN FIRST_HALF => -- if the input data doesn't exceeds the output data vector width
c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
c_v_count := c_v_count + 1; -- increase the counter of c_v with 1
out_sosi.valid <= '0'; -- out_sosi.valid 0
IF rst = '1' THEN
state := RESET;
ELSIF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) AND (out_data_count = 0) THEN
state := SECOND_HALF;
ELSIF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) AND (out_data_count = 1) THEN
state := OVER_FLOW;
ELSE
state := FIRST_HALF;
END IF;
WHEN SECOND_HALF => -- if the input data exceeds output data vector width but not the c_v width
c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
c_v_count := c_v_count + 1; -- increase the counter of c_v with 1
out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(c_out_data_w - 1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
out_sosi.valid <= '1'; -- out_sosi.valid 1
out_data_count := out_data_count + 1; -- increase the counter of out_sosi.data with 1
END IF;
ELSE -- if the input data doesn't exceeds the output data vector width
c_v(g_in_data_w * (c_v_count + 1) + a_of - 1 DOWNTO g_in_data_w * c_v_count + a_of) := in_data(g_in_data_w - 1 DOWNTO 0); -- fill c_v
c_v_count := c_v_count + 1; -- increase the counter of c_v with 1
out_sosi.valid <= '0'; -- out_sosi.valid 0
END IF;
IF rst = '1' THEN
state := RESET;
ELSIF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) AND (out_data_count = 0) THEN
state := SECOND_HALF;
ELSIF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) AND (out_data_count = 1) THEN
state := OVER_FLOW;
ELSE
state := FIRST_HALF;
END IF;
WHEN OVER_FLOW => -- if the input data exceeds the output data vector width and the c_v width
a_of := a_of + (g_in_data_w*(c_v_count+1)) - (c_out_data_w*(out_data_count+1)); -- check how much overflow there is and safe it in a_of
out_of <= a_of; -- set the output overflow to the overflow that maches the out_sosi.data vector
c_v(k_c_v_w - 1 DOWNTO k_c_v_w-(g_in_data_w - a_of)) := in_data(g_in_data_w - a_of - 1 DOWNTO 0); -- fill the rest of c_v untill the end
c_v(a_of - 1 DOWNTO 0) := in_data(g_in_data_w - 1 DOWNTO g_in_data_w - a_of); -- fill the start of c_v untill the a_of
out_sosi.data(c_out_data_w - 1 DOWNTO 0) <= c_v(k_c_v_w - 1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
out_sosi.valid <= '1'; -- out_sosi.valid 1
c_v_count := 0; -- reset counter
out_data_count := 0; -- reset counter
IF rst = '1' THEN
state := RESET;
ELSIF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) AND (out_data_count = 0) THEN
state := SECOND_HALF;
ELSIF ((g_in_data_w*(c_v_count+1))+a_of >= c_out_data_w*(out_data_count+1)) AND (out_data_count = 1) THEN
state := OVER_FLOW;
ELSE
state := FIRST_HALF;
END IF;
WHEN RESET =>
a_of := 0;
c_v := (OTHERS => '0');
c_v_count := 0;
out_data_count := 0;
out_of <= 0;
out_sosi <= c_dp_sosi_init;
IF rst = '1' THEN
state := RESET;
ELSE
state := FIRST_HALF;
END IF;
END CASE;
END IF;
END PROCESS;
END rtl;
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+ 64
− 57
View file @ 41ffb62e
......@@ -35,11 +35,11 @@ USE common_lib.common_pkg.ALL;
ENTITY tb_ddrctrl IS
GENERIC (
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
g_nof_streams : POSITIVE := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
g_sim_length : NATURAL := 52
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
g_nof_streams : POSITIVE := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
g_sim_length : NATURAL := 52
);
END tb_ddrctrl;
......@@ -47,14 +47,14 @@ END tb_ddrctrl;
ARCHITECTURE tb OF tb_ddrctrl IS
-- constants for testbench
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
-- constants for readability
CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
CONSTANT c_adr_w : NATURAL := 4; -- address with in simulation
CONSTANT c_adr_size : NATURAL := 2**c_adr_w; -- address size in simulation
CONSTANT c_in_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- output data vector with, 576
CONSTANT c_adr_w : NATURAL := 4; -- address with in simulation
CONSTANT c_adr_size : NATURAL := 2**c_adr_w; -- address size in simulation
-- function for making total data vector
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
......@@ -67,27 +67,27 @@ ARCHITECTURE tb OF tb_ddrctrl IS
END FUNCTION c_total_vector_init;
-- constant for running the test
CONSTANT c_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
CONSTANT c_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0) := c_total_vector_init; -- vector which contains all input data vectors to make it easy to fill ctr_vector
-- input signals for ddrctrl.vhd
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '0';
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '0';
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input data signal for ddrctrl_pack.vhd
-- output singals from ddrctrl.vhd
SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is
SIGNAL out_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst; -- output signal from ddrctrl_pack.vhd
SIGNAL out_of : NATURAL := 0; -- output signal from ddrctrl_repack to determen how high the overflow is
SIGNAL out_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst; -- output signal from ddrctrl_pack.vhd
-- testbench signal
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
-- signals for running test
SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest
SIGNAL d_lag_due_reset : NATURAL := 0;
SIGNAL d_rst : STD_LOGIC := '0';
SIGNAL in_data_cnt : NATURAL := 0; -- signal which contains the amount of times there has been input data for ddrctrl_repack.vhd
SIGNAL test_running : STD_LOGIC := '0'; -- signal to tell wheter the testing has started
SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest
SIGNAL q_lag_due_reset : NATURAL := 0;
SIGNAL q_rst : STD_LOGIC := '0';
BEGIN
......@@ -100,10 +100,18 @@ BEGIN
-- start the test
tb_end <= '0';
WAIT UNTIL rising_edge(clk);
WAIT UNTIL out_of /= 0;
WAIT UNTIL out_of = 0;
test_running <= '1';
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*5;
rst <= '1';
WAIT FOR c_clk_period*1;
rst <= '0';
IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
ELSE
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
END IF;
WAIT FOR c_clk_period*1;
test_running <= '1'; -- start of test
-- filling the input data vectors with the corresponding numbers
make_data : FOR J IN 0 TO g_sim_length-1 LOOP
......@@ -115,49 +123,48 @@ BEGIN
END LOOP;
test_running <= '0';
-- testing reset
FOR I IN 0 TO g_sim_length-1 LOOP
rst <= '1';
WAIT FOR c_clk_period*1;
rst <= '0';
IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
ELSE
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
END IF;
WAIT FOR c_clk_period*((((c_out_data_w / c_in_data_w)+1)*c_adr_size)+4);
END LOOP;
-- stopping the testbench
WAIT FOR c_clk_period*5;
tb_end <= '1';
ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
-- excecuting the reset test
p_test_reset : PROCESS
BEGIN
rst <= '0';
--WAIT FOR c_clk_period*1;
IF lag_due_reset + TO_UINT(out_mosi.address) >= c_adr_size THEN
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address)-c_adr_size;
ELSE
lag_due_reset <= lag_due_reset+TO_UINT(out_mosi.address);
END IF;
WAIT FOR c_clk_period*(c_adr_size+3);
rst <= '1';
WAIT FOR c_clk_period*1;
END PROCESS;
-- generating compare data for out_mosi
p_out_mosi : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
if rising_edge(clk) THEN
d_lag_due_reset <= lag_due_reset;
d_rst <= rst;
q_lag_due_reset <= lag_due_reset;
q_rst <= rst;
END IF;
END PROCESS;
-- verifying if the address is correct by keeping trach of the address
-- verifying if the address is correct by keeping track of the address
p_verify_address : PROCESS
BEGIN
FOR I IN 0 TO c_adr_size-1 LOOP
WAIT UNTIL out_mosi.wr = '1';
IF d_rst = '1' THEN
IF q_rst = '1' THEN
WAIT UNTIL out_mosi.wr = '1';
END IF;
IF I >= d_lag_due_reset THEN
ASSERT I-d_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-d_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
IF I >= q_lag_due_reset THEN
ASSERT I-q_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ELSE
ASSERT (I-d_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-d_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
END IF;
END LOOP;
END PROCESS;
......@@ -169,15 +176,15 @@ BEGIN
VARIABLE out_data_cnt : NATURAL := 0;
BEGIN
WAIT UNTIL out_mosi.wr = '1' AND test_running = '1';
IF out_data_cnt >= 1 THEN
IF out_data_cnt mod 2 = 0 THEN
ctr_of := c_in_data_w*(in_data_cnt-1)-c_out_data_w*out_data_cnt;
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
END IF;
ASSERT out_mosi.wrdata(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
WAIT UNTIL test_running = '1';
WAIT UNTIL out_mosi.wr = '1';
out_data_cnt := out_data_cnt+1;
IF out_data_cnt mod 2 = 0 THEN
assert false report "in_data_cnt = " & NATURAL'image(in_data_cnt) & ", out_data_cnt = " & NATURAL'image(out_data_cnt) severity note;
ctr_of := c_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
END IF;
out_data_cnt := out_data_cnt+1;
ASSERT out_mosi.wrdata(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END PROCESS;
......
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd
+ 16
− 16
View file @ 41ffb62e
......@@ -55,6 +55,7 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
-- input signals for ddrctrl_address_counter.vhd
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC := '0';
SIGNAL q_rst : STD_LOGIC := '0';
SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_init; -- signal which is the input for ddrctrl_address_counter.vhd
-- output signal from ddrctrl_address_counter.vhd
......@@ -63,12 +64,11 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
-- testbench signals
SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
SIGNAL in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS => '0'); -- signal which contains the data that is set as input
SIGNAL d_in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL q_in_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS => '0'); -- signal which contains the data that is set as input with a delay of 1 clockcycle
SIGNAL in_data_enable : STD_LOGIC := '0'; -- signal to determen if in_data is ready for reading
SIGNAL d_in_data_enable : STD_LOGIC := '0';
SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a rest
SIGNAL d_lag_due_reset : NATURAL := 0;
SIGNAL d_rst : STD_LOGIC := '0';
SIGNAL q_in_data_enable : STD_LOGIC := '0'; -- signal to determen if in_data is ready for reading with a delay of 1 clockcycle
SIGNAL lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a reset
SIGNAL q_lag_due_reset : NATURAL := 0; -- signal to hold the address lag after a reset with a delay of 1 clockcycle
BEGIN
......@@ -109,10 +109,10 @@ BEGIN
BEGIN
WAIT UNTIL rising_edge(clk);
if rising_edge(clk) THEN
d_in_data_enable <= in_data_enable;
d_in_data <= in_data;
d_lag_due_reset <= lag_due_reset;
d_rst <= rst;
q_in_data_enable <= in_data_enable;
q_in_data <= in_data;
q_lag_due_reset <= lag_due_reset;
q_rst <= rst;
END IF;
END PROCESS;
......@@ -122,8 +122,8 @@ BEGIN
BEGIN
WAIT UNTIL rising_edge(clk);
IF rising_edge(clk) THEN
ASSERT d_in_data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR;
ASSERT d_in_data_enable = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
ASSERT q_in_data(c_data_w-1 DOWNTO 0) = out_mosi.wrdata(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata" SEVERITY ERROR;
ASSERT q_in_data_enable = out_mosi.wr REPORT "in_sosi.valid does not match out_mosi.wr" SEVERITY ERROR;
END IF;
END PROCESS;
......@@ -142,18 +142,18 @@ BEGIN
WAIT FOR c_clk_period*1;
END PROCESS;
-- verifying if the address is correct by keeping trach of the address
-- verifying if the address is correct by keeping track of the address
p_verify_address : PROCESS
BEGIN
FOR I IN 0 TO c_adr_size-1 LOOP
WAIT UNTIL out_mosi.wr = '1';
IF d_rst = '1' THEN
IF q_rst = '1' THEN
WAIT UNTIL out_mosi.wr = '1';
END IF;
IF I >= d_lag_due_reset THEN
ASSERT I-d_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-d_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
IF I >= q_lag_due_reset THEN
ASSERT I-q_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ELSE
ASSERT (I-d_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-d_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR;
END IF;
END LOOP;
END PROCESS;
......
applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_repack.vhd
+ 15
− 10
View file @ 41ffb62e
......@@ -67,6 +67,7 @@ ARCHITECTURE tb OF tb_ddrctrl_repack IS
-- input signals for ddrctrl_repack.vhd
SIGNAL clk : STD_LOGIC := '1'; -- clock signal
SIGNAL rst : STD_LOGIC := '0'; -- reset signal
SIGNAL in_data : STD_LOGIC_VECTOR(g_in_data_w-1 DOWNTO 0) := (OTHERS => '0'); -- input data signal for ddrctrl_repack
-- output signals from ddrctrl_repack.vhd
......@@ -92,8 +93,11 @@ BEGIN
-- start the test
tb_end <= '0';
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT UNTIL out_of /= 0; -- wait for out_of /= 0 to align to ddrctrl_repack properly
WAIT UNTIL out_of = 0; -- align to ddrctrl_repack
WAIT FOR c_clk_period*5;
rst <= '1';
WAIT FOR c_clk_period*1;
rst <= '0';
WAIT FOR c_clk_period*1;
test_running <= '1'; -- start of test
-- filling the input vector g_sim_lengt amount of times
......@@ -117,15 +121,15 @@ BEGIN
VARIABLE out_data_cnt : NATURAL := 0;
BEGIN
WAIT UNTIL out_sosi.valid = '1' AND test_running = '1';
IF out_data_cnt >= 1 THEN
IF out_data_cnt mod 2 = 0 THEN
ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
END IF;
ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END IF;
WAIT UNTIL test_running = '1';
WAIT UNTIL out_sosi.valid = '1';
out_data_cnt := out_data_cnt+1;
IF out_data_cnt mod 2 = 0 THEN
assert false report "in_data_cnt = " & NATURAL'image(in_data_cnt) & ", out_data_cnt = " & NATURAL'image(out_data_cnt) severity note;
ctr_of := g_in_data_w*in_data_cnt-c_out_data_w*out_data_cnt;
ASSERT ctr_of = out_of REPORT "The amount of overflow does not match, ctr_of = " & NATURAL'image(ctr_of) & ", out_of = " & NATURAL'image(out_of) SEVERITY ERROR;
END IF;
ASSERT out_sosi.data(c_out_data_w-1 DOWNTO 0) = c_total_vector(c_out_data_w*out_data_cnt-1 DOWNTO c_out_data_w*(out_data_cnt-1)) REPORT "Data does not match, out_data_cnt = " & NATURAL'image(out_data_cnt) SEVERITY ERROR;
END PROCESS;
......@@ -137,6 +141,7 @@ BEGIN
)
PORT MAP (
clk => clk,
rst => rst,
in_data => in_data,
out_of => out_of,
......
boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+ 1
− 1
View file @ 41ffb62e
......@@ -33,7 +33,7 @@ PACKAGE dp_stream_pkg Is
-- Remarks:
-- * Choose smallest maximum SOSI slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
-- * The large SOSI data field width of 256b has some disadvantages:
-- . about 10% extra simulation time and PC memory usage compared to 72b (measured using tb_unb_tse_board)
-- . about 1ni0% extra simulation time and PC memory usage compared to 72b (measured using tb_unb_tse_board)
-- . a 256b number has 64 hex digits in the Wave window which is awkward because of the leading zeros when typically
-- only 32b are used, fortunately integer representation still works OK (except 0 which is shown as blank).
-- However the alternatives are not attractive, because they affect the implementation of the streaming
......
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