- Pointing to RadioHDL DDR3 phy.

- renmaed sopc file

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

 hdl_lib_name = unb1_ddr3
 hdl_library_clause_name = unb1_ddr3_lib
-hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
+hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth diagnostics io_ddr tech_ddr
 hdl_lib_uses_sim = 
-
 hdl_lib_technology = ip_stratixiv
+hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
 
 build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
-    $HDL_BUILD_DIR/quartus/unb1_ddr3/sopc_unb_ddr3.vhd
+    $HDL_BUILD_DIR/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
     src/vhdl/node_unb1_ddr3.vhd
     src/vhdl/mmm_unb1_ddr3.vhd
     src/vhdl/unb1_ddr3.vhd
     
 test_bench_files = 
+    tb/vhdl/tb_unb1_ddr3.vhd
 
 synth_top_level_entity =
 
@@ -31,7 +32,20 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/quartus/unb1_ddr3/sopc_unb_ddr3.qip
-    $UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master.qip
-    $UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_slave.qip
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $HDL_BUILD_DIR/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    
+modelsim_search_libraries =
+# stratixiv only
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip
+# arria10 only
+#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+#    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip
+# both (will yield errors if the technology library is not available in simulator but these errors can be ignored)
+#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+#    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip     twentynm     twentynm_hssi     twentynm_hip