Ready for review.

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd

@@ -103,7 +103,7 @@ BEGIN
 
     CASE q_reg.state IS
     WHEN RESET =>
-      v.s_adr := c_max_adr-1;
+      v.s_adr := c_max_adr-1;                                                                                                             -- when there is a reset the fifo in io_ddr always needs the first out_sosi.valid to stop flushing the data so the first data word always gets lost. if s_adr is set to 0 after a restart the word from s_adr 1 will be put at address 0 in memory.
 
     WHEN COUNTING =>
       v.s_adr := q_reg.s_adr+1;