Define c_mm_reg_adr_w = 2.

libraries/base/dp/src/vhdl/mms_dp_force_data_arr.vhd

@@ -69,6 +69,8 @@ END mms_dp_force_data_arr;
 
 ARCHITECTURE str OF mms_dp_force_data_arr IS
 
+  CONSTANT c_mm_reg_adr_w : NATURAL := 2;  -- copied from mms_dp_force_data.vhd
+
   SIGNAL reg_force_data_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
   SIGNAL reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
   
@@ -77,7 +79,7 @@ BEGIN
   u_mem_mux : ENTITY common_lib.common_mem_mux
   GENERIC MAP (    
     g_nof_mosi    => g_nof_streams,
-    g_mult_addr_w => 2
+    g_mult_addr_w => c_mm_reg_adr_w
   )
   PORT MAP (
     mosi     => reg_force_data_mosi,