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Commit 40826c7f authored by Eric Kooistra's avatar Eric Kooistra
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Added hdl_lib_technology key using mode=1 in hdl_config.py

parent 55a2dcb1
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hdl_lib_name = ip_arria10 hdl_lib_name = ip_arria10
hdl_library_clause_name = ip_arria10_lib hdl_library_clause_name = ip_arria10_lib
hdl_lib_uses = technology hdl_lib_uses = technology
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
hdl_lib_name = ip_stratixiv hdl_lib_name = ip_stratixiv
hdl_library_clause_name = ip_stratixiv_lib hdl_library_clause_name = ip_stratixiv_lib
hdl_lib_uses = technology numonyx_m25p128 hdl_lib_uses = technology numonyx_m25p128
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
hdl_lib_name = ip_stratixiv_tse_sgmii_gx hdl_lib_name = ip_stratixiv_tse_sgmii_gx
hdl_library_clause_name = ip_stratixiv_tse_sgmii_gx_lib hdl_library_clause_name = ip_stratixiv_tse_sgmii_gx_lib
hdl_lib_uses = technology hdl_lib_uses = technology
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
hdl_lib_name = ip_stratixiv_tse_sgmii_lvds hdl_lib_name = ip_stratixiv_tse_sgmii_lvds
hdl_library_clause_name = ip_stratixiv_tse_sgmii_lvds_lib hdl_library_clause_name = ip_stratixiv_tse_sgmii_lvds_lib
hdl_lib_uses = common hdl_lib_uses = common
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
hdl_lib_name = ip_virtex4 hdl_lib_name = ip_virtex4
hdl_library_clause_name = ip_virtex4_lib hdl_library_clause_name = ip_virtex4_lib
hdl_lib_uses = hdl_lib_uses =
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
hdl_lib_name = tech_memory hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib hdl_library_clause_name = tech_memory_lib
hdl_lib_uses = technology ip_stratixiv ip_arria10 ip_virtex4 hdl_lib_uses = technology ip_stratixiv ip_arria10 ip_virtex4
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
hdl_lib_name = tech_transceiver hdl_lib_name = tech_transceiver
hdl_library_clause_name = tech_transceiver_lib hdl_library_clause_name = tech_transceiver_lib
hdl_lib_uses = technology ip_stratixiv common dp hdl_lib_uses = technology ip_stratixiv common dp
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
hdl_lib_name = tech_tse hdl_lib_name = tech_tse
hdl_library_clause_name = tech_tse_lib hdl_library_clause_name = tech_tse_lib
hdl_lib_uses = technology ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx common dp hdl_lib_uses = technology ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx common dp
hdl_lib_technology =
build_sim_dir = $HDL_BUILD_DIR build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR build_synth_dir = $HDL_BUILD_DIR
......
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