Changed c_ into g_. Import common.py as cm. This also means that in the...

Changed c_ into g_. Import common.py as cm. This also means that in the peripheral YAML files cm.c_nof_complex and cm.celi_log2() habe to be used.

tools/oneclick/prestudy/YAML/bf_unit/peripheral.cfg

@@ -4,28 +4,28 @@ peripheral_name: bf_unit
 nof_inst: 1
 
 parameters:
-  c_weights_w:                    16
-  c_nof_weights:                 256
-  c_nof_signal_paths:             64  
-  c_nof_subbands:                 24  
-  c_nof_input_streams:            16
-  c_nof_signal_paths_per_stream:   4
+  g_weights_w:                    16
+  g_nof_weights:                 256
+  g_nof_signal_paths:             64  
+  g_nof_subbands:                 24  
+  g_nof_input_streams:            16
+  g_nof_signal_paths_per_stream:   4
 
 ram_bf_weights:
-  width: c_weights_w*c_nof_complex
-  depth: c_nof_weights*c_nof_signal_paths # 256*64 = 16384
+  width: g_weights_w*cm.c_nof_complex
+  depth: g_nof_weights*g_nof_signal_paths # 256*64 = 16384
   mode:  RW   
   descr: "Contains the weights. The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
   
 ram_ss_ss_wide: 
-  width: ceil_log2(c_nof_subbands*c_nof_signal_paths_per_stream)
-  depth: c_nof_weights*c_nof_input_streams*c_nof_signal_paths_per_stream #256*16*4 # nof_weights*nof_input_streams*nof_signal_paths_per_stream = 256*16*4=16384
+  width: cm.ceil_log2(g_nof_subbands*g_nof_signal_paths_per_stream)
+  depth: g_nof_weights*g_nof_input_streams*g_nof_signal_paths_per_stream #256*16*4 # nof_weights*nof_input_streams*nof_signal_paths_per_stream = 256*16*4=16384
   mode:  RW   
   descr: "Contains the addresses to select from the stored subbands."
 
 ram_st_sst_bf: 
   width: 56
-  depth: c_nof_weights*c_nof_complex   # 256*2=512
+  depth: g_nof_weights*cm.c_nof_complex   # 256*2=512
   mode:  RO   
   descr: "Contains the weights. The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."