initial

applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/filters.xml

+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="11.1sp2" />

applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/.qsys_edit/preferences.xml

+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="Default">
+  <columns>
+   <connections preferredWidth="63" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <clocktable>
+  <columns>
+   <clockname preferredWidth="324" />
+   <clocksource preferredWidth="323" />
+   <frequency preferredWidth="304" />
+  </columns>
+ </clocktable>
+ <library expandedCategories="Library,Project,Library/Uniboard" />
+ <window width="1262" height="1079" x="0" y="0" />
+ <hdlexample language="VHDL" />
+ <generation simulation="VHDL" testbench_system="NONE" />
+</preferences>

applications/apertif/designs/apertif_unb1_cor_mesh_ref/quartus/apertif_unb1_cor_mesh_ref_pins.tcl

+# Pin files
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_mesh_tr_clk_pin.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/FRONT_NODE_mesh_nocmu_pins.tcl
\ No newline at end of file