Added proc_common_dclk_generate_sclk()

libraries/base/common/src/vhdl/common_pkg.vhd

@@ -429,6 +429,11 @@ PACKAGE common_pkg IS
   FUNCTION func_common_reorder2_get_select(I, J, N : NATURAL; select_arr : t_natural_arr) RETURN NATURAL;
   FUNCTION func_common_reorder2_inverse_select(N : NATURAL; select_arr : t_natural_arr) RETURN t_natural_arr;
   
+  -- Generate faster sample SCLK from digital DCLK for sim only
+  PROCEDURE proc_common_dclk_generate_sclk(CONSTANT Pfactor : IN    POSITIVE;
+                                           SIGNAL   dclk    : IN    STD_LOGIC;
+                                           SIGNAL   sclk    : INOUT STD_LOGIC);
+  
 END common_pkg;
 
 PACKAGE BODY common_pkg IS
@@ -2200,5 +2205,57 @@ PACKAGE BODY common_pkg IS
     RETURN v_inverse_arr;
   END func_common_reorder2_inverse_select;
   
+  ------------------------------------------------------------------------------
+  -- PROCEDURE: Generate faster sample SCLK from digital DCLK for sim only
+  -- Description:
+  --   The SCLK kan be used to serialize Pfactor >= 1 symbols per word and then 
+  --   view them in a scope component that is use internally in the design.
+  --   The scope component is only instantiated for simulation, to view the
+  --   serialized symbols, typically with decimal radix and analogue format.
+  --   The scope component will not be synthesized, because the SCLK can not
+  --   be synthesized.
+  --   
+  --   Pfactor = 4
+  --            _______         _______         _______         _______
+  --   DCLK ___|       |_______|       |_______|       |_______|       |_______
+  --        ___________________   _   _   _   _   _   _   _   _   _   _   _   _
+  --   SCLK                    |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
+  --
+  --   The rising edges of SCLK occur after the rising edge of DCLK, to ensure
+  --   that they all apply to the same wide data word that was clocked by the
+  --   rising edge of the DCLK.
+  ------------------------------------------------------------------------------
+  PROCEDURE proc_common_dclk_generate_sclk(CONSTANT Pfactor : IN    POSITIVE;
+                                           SIGNAL   dclk    : IN    STD_LOGIC;
+                                           SIGNAL   sclk    : INOUT STD_LOGIC) IS
+    VARIABLE v_dperiod : TIME;
+    VARIABLE v_speriod : TIME;
+  BEGIN
+    SCLK <= '1';
+    -- Measure DCLK period
+    WAIT UNTIL rising_edge(DCLK);
+    v_dperiod := NOW;
+    WAIT UNTIL rising_edge(DCLK);
+    v_dperiod := NOW - v_dperiod;
+    v_speriod := v_dperiod / Pfactor;
+    -- Generate Pfactor SCLK periods per DCLK period
+    WHILE TRUE LOOP
+      -- Realign at every DCLK
+      WAIT UNTIL rising_edge(DCLK);
+      -- Create Pfactor SCLK periods within this DCLK period
+      SCLK <= '0';
+      IF Pfactor>1 THEN
+        FOR I IN 0 TO 2*Pfactor-1-2 LOOP
+          WAIT FOR v_speriod/2;
+          SCLK <= NOT SCLK;
+        END LOOP;
+      END IF;
+      WAIT FOR v_speriod/2;
+      SCLK <= '1';
+      -- Wait for next DCLK
+    END LOOP;
+    WAIT;
+  END proc_common_dclk_generate_sclk;
+  
 END common_pkg;