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RTSD
HDL
Commits
3ef966a0
Commit
3ef966a0
authored
Dec 8, 2014
by
Eric Kooistra
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Use same ports for sim_xaui as for tech_xaui.
parent
e24fbb29
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libraries/technology/xaui/sim_xaui.vhd
+20
-6
20 additions, 6 deletions
libraries/technology/xaui/sim_xaui.vhd
with
20 additions
and
6 deletions
libraries/technology/xaui/sim_xaui.vhd
+
20
−
6
View file @
3ef966a0
...
...
@@ -23,6 +23,7 @@
LIBRARY
IEEE
,
common_lib
,
tech_transceiver_lib
;
USE
IEEE
.
STD_LOGIC_1164
.
ALL
;
USE
common_lib
.
common_pkg
.
ALL
;
USE
common_lib
.
common_mem_pkg
.
ALL
;
USE
common_lib
.
common_interface_layers_pkg
.
ALL
;
ENTITY
sim_xaui
IS
...
...
@@ -34,6 +35,17 @@ ENTITY sim_xaui IS
tr_clk
:
IN
STD_LOGIC
;
-- 156.25 MHz
tr_rst
:
IN
STD_LOGIC
;
-- Calibration & reconfig clock
cal_rec_clk
:
IN
STD_LOGIC
:
=
'0'
;
-- not used in model, but available to have same port map as tech_xaui
-- MM interface
mm_clk
:
IN
STD_LOGIC
:
=
'0'
;
-- not used in model, but available to have same port map as tech_xaui
mm_rst
:
IN
STD_LOGIC
:
=
'0'
;
xaui_mosi
:
IN
t_mem_mosi
:
=
c_mem_mosi_rst
;
xaui_miso
:
OUT
t_mem_miso
;
-- XGMII interface
tx_clk_arr
:
IN
STD_LOGIC_VECTOR
(
g_nof_xaui
-1
DOWNTO
0
);
-- 156.25 MHz, externally connect tr_clk to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
rx_clk_arr_out
:
OUT
STD_LOGIC_VECTOR
(
g_nof_xaui
-1
DOWNTO
0
);
-- recovered clock per XAUI, rx_clk_arr = tx_clk_arr in this model
rx_clk_arr_in
:
IN
STD_LOGIC_VECTOR
(
g_nof_xaui
-1
DOWNTO
0
);
-- externally connect to rx_clk_arr_out to avoid clock delta-delay
...
...
@@ -43,11 +55,12 @@ ENTITY sim_xaui IS
txc_rx_channelaligned_arr
:
OUT
STD_LOGIC_VECTOR
(
g_nof_xaui
-1
DOWNTO
0
);
-- Serial I/O
xgmii_tx_dc_arr
:
IN
t_xgmii_dc_arr
(
g_nof_xaui
-1
DOWNTO
0
);
xgmii_rx_dc_arr
:
OUT
t_xgmii_dc_arr
(
g_nof_xaui
-1
DOWNTO
0
);
xaui_
r
x_arr
:
IN
t_xaui_arr
(
g_nof_xaui
-1
DOWNTO
0
);
xaui_
t
x_arr
:
OUT
t_xaui_arr
(
g_nof_xaui
-1
DOWNTO
0
)
xaui_
t
x_arr
:
OUT
t_xaui_arr
(
g_nof_xaui
-1
DOWNTO
0
);
xaui_
r
x_arr
:
IN
t_xaui_arr
(
g_nof_xaui
-1
DOWNTO
0
)
);
END
sim_xaui
;
...
...
@@ -71,6 +84,9 @@ BEGIN
-- Model rx_clk = tx_clk = tr_clk
rx_clk_arr_out
<=
tx_clk_arr
;
-- No MM model
xaui_miso
<=
c_mem_miso_rst
;
gen_nof_xaui
:
FOR
i
IN
g_nof_xaui
-1
DOWNTO
0
GENERATE
-- Rewire XGMII
...
...
@@ -123,7 +139,6 @@ BEGIN
g_line_rate
=>
c_xaui_serdes_line_rate
)
PORT
MAP
(
tr_clk
=>
tr_clk
,
tr_rst
=>
tr_rst
,
...
...
@@ -139,7 +154,6 @@ BEGIN
g_line_rate
=>
c_xaui_serdes_line_rate
)
PORT
MAP
(
tr_clk
=>
tr_clk
,
tr_rst
=>
tr_rst
,
...
...
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