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Commit 3d197edc authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added dp_xonoff_iab_i register.

parent 7f0fb5c3
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applications/arts/designs/arts_unb1_sc4/quartus/qsys_mm_master.qsys
+ 165
− 87
View file @ 3d197edc
......@@ -16,7 +16,7 @@
{
datum baseAddress
{
value = "1248";
value = "1504";
type = "long";
}
}
......@@ -85,152 +85,152 @@
type = "boolean";
}
}
element reg_tr_xaui.mem
element reg_dp_offload_tx_iab_i_hdr_dat.mem
{
datum baseAddress
{
value = "8192";
value = "1024";
type = "long";
}
}
element ram_bf_unit_x_ss_ss_wide.mem
element ram_bf_unit_x_st_sst.mem
{
datum baseAddress
{
value = "1344";
value = "1632";
type = "long";
}
}
element reg_dp_gain_i.mem
element reg_dp_offload_rx_hdr_dat.mem
{
datum baseAddress
{
value = "2048";
value = "512";
type = "long";
}
}
element reg_dp_gain_q.mem
element rom_unb_system_info.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "2052";
value = "4096";
type = "long";
}
}
element reg_dp_xonoff_tab_iquv.mem
element reg_dp_offload_tx_tab_i_hdr_dat.mem
{
datum baseAddress
{
value = "1272";
value = "768";
type = "long";
}
}
element reg_dp_gain_u.mem
element reg_remu.mem
{
datum baseAddress
{
value = "2056";
value = "1312";
type = "long";
}
}
element pio_system_info.mem
{
datum _lockedAddress
element reg_dp_xonoff_output.mem
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "0";
value = "1752";
type = "long";
}
}
element reg_dp_xonoff_output.mem
element reg_wdi.mem
{
datum baseAddress
{
value = "1752";
value = "1520";
type = "long";
}
}
element reg_remu.mem
element reg_dp_gain_q.mem
{
datum baseAddress
{
value = "1056";
value = "1556";
type = "long";
}
}
element reg_dp_xonoff_tab_i.mem
element reg_mdio_0.mem
{
datum baseAddress
{
value = "1280";
value = "1408";
type = "long";
}
}
element reg_mdio_2.mem
element reg_dp_offload_tx_tab_iquv_hdr_dat.mem
{
datum baseAddress
{
value = "1088";
value = "512";
type = "long";
}
}
element reg_wdi.mem
element reg_dp_gain_v.mem
{
datum baseAddress
{
value = "1264";
value = "1564";
type = "long";
}
}
element reg_dp_offload_tx_tab_i_hdr_dat.mem
element ram_bf_unit_x_bf_weights.mem
{
datum baseAddress
{
value = "768";
value = "128";
type = "long";
}
}
element reg_ppsh.mem
element reg_dp_xonoff_tab_iquv.mem
{
datum baseAddress
{
value = "1256";
value = "1528";
type = "long";
}
}
element reg_dp_offload_tx_iab_i_hdr_dat.mem
element reg_mdio_1.mem
{
datum baseAddress
{
value = "1792";
value = "1376";
type = "long";
}
}
element reg_dp_gain_v.mem
element reg_dp_gain_u.mem
{
datum baseAddress
{
value = "2060";
value = "1560";
type = "long";
}
}
element ram_bf_unit_x_st_sst.mem
element reg_dp_xonoff_iab_i.mem
{
datum baseAddress
{
value = "1632";
value = "1544";
type = "long";
}
}
element reg_bf_unit_x_st_sst.mem
element reg_dp_bsn_align_mesh.mem
{
datum baseAddress
{
value = "1024";
value = "1440";
type = "long";
}
}
......@@ -242,40 +242,35 @@
type = "long";
}
}
element reg_mdio_1.mem
element reg_dp_xonoff_tab_i.mem
{
datum baseAddress
{
value = "1120";
value = "1536";
type = "long";
}
}
element reg_dp_offload_tx_tab_iquv_hdr_dat.mem
element reg_bf_unit_x_st_sst.mem
{
datum baseAddress
{
value = "512";
value = "1024";
type = "long";
}
}
element rom_unb_system_info.mem
{
datum _lockedAddress
element reg_dp_bsn_align_input.mem
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "4096";
value = "1488";
type = "long";
}
}
element reg_dp_offload_rx_hdr_dat.mem
element reg_dp_gain_i.mem
{
datum baseAddress
{
value = "512";
value = "1552";
type = "long";
}
}
......@@ -283,47 +278,47 @@
{
datum baseAddress
{
value = "1024";
value = "1280";
type = "long";
}
}
element reg_dp_bsn_align_input.mem
element reg_tr_xaui.mem
{
datum baseAddress
{
value = "1232";
value = "8192";
type = "long";
}
}
element reg_mdio_0.mem
element ram_bf_unit_x_ss_ss_wide.mem
{
datum baseAddress
{
value = "1152";
value = "1344";
type = "long";
}
}
element reg_dp_bsn_align_mesh.mem
element reg_unb_sens.mem
{
datum baseAddress
{
value = "1184";
value = "224";
type = "long";
}
}
element ram_bf_unit_x_bf_weights.mem
element reg_mdio_2.mem
{
datum baseAddress
{
value = "128";
value = "1344";
type = "long";
}
}
element reg_unb_sens.mem
element reg_ppsh.mem
{
datum baseAddress
{
value = "224";
value = "1512";
type = "long";
}
}
......@@ -335,6 +330,19 @@
type = "long";
}
}
element pio_system_info.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "0";
type = "long";
}
}
element avs_eth_0.mms_ram
{
datum baseAddress
......@@ -546,6 +554,14 @@
type = "boolean";
}
}
element reg_dp_xonoff_iab_i
{
datum _sortIndex
{
value = "37";
type = "int";
}
}
element reg_dp_xonoff_output
{
datum _sortIndex
......@@ -688,7 +704,7 @@
{
datum baseAddress
{
value = "1216";
value = "1472";
type = "long";
}
}
......@@ -720,7 +736,7 @@
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1491826440798" />
<parameter name="timeStamp" value="1492094862468" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
......@@ -1653,6 +1669,41 @@
internal="reg_dp_gain_v.readdata"
type="conduit"
dir="end" />
<interface
name="reg_dp_xonoff_iab_i_reset"
internal="reg_dp_xonoff_iab_i.reset"
type="conduit"
dir="end" />
<interface
name="reg_dp_xonoff_iab_i_clk"
internal="reg_dp_xonoff_iab_i.clk"
type="conduit"
dir="end" />
<interface
name="reg_dp_xonoff_iab_i_address"
internal="reg_dp_xonoff_iab_i.address"
type="conduit"
dir="end" />
<interface
name="reg_dp_xonoff_iab_i_write"
internal="reg_dp_xonoff_iab_i.write"
type="conduit"
dir="end" />
<interface
name="reg_dp_xonoff_iab_i_writedata"
internal="reg_dp_xonoff_iab_i.writedata"
type="conduit"
dir="end" />
<interface
name="reg_dp_xonoff_iab_i_read"
internal="reg_dp_xonoff_iab_i.read"
type="conduit"
dir="end" />
<interface
name="reg_dp_xonoff_iab_i_readdata"
internal="reg_dp_xonoff_iab_i.readdata"
type="conduit"
dir="end" />
<module
kind="altera_avalon_onchip_memory2"
version="11.1"
......@@ -1811,7 +1862,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_tab_iquv_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_dp_offload_tx_tab_i_hdr_dat.mem' start='0x300' end='0x400' /><slave name='reg_epcs.mem' start='0x400' end='0x420' /><slave name='reg_remu.mem' start='0x420' end='0x440' /><slave name='reg_mdio_2.mem' start='0x440' end='0x460' /><slave name='reg_mdio_1.mem' start='0x460' end='0x480' /><slave name='reg_mdio_0.mem' start='0x480' end='0x4A0' /><slave name='reg_dp_bsn_align_mesh.mem' start='0x4A0' end='0x4C0' /><slave name='pio_wdi.s1' start='0x4C0' end='0x4D0' /><slave name='reg_dp_bsn_align_input.mem' start='0x4D0' end='0x4E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x4E0' end='0x4E8' /><slave name='reg_ppsh.mem' start='0x4E8' end='0x4F0' /><slave name='reg_wdi.mem' start='0x4F0' end='0x4F8' /><slave name='reg_dp_xonoff_tab_iquv.mem' start='0x4F8' end='0x500' /><slave name='reg_dp_xonoff_tab_i.mem' start='0x500' end='0x508' /><slave name='reg_dp_offload_tx_iab_i_hdr_dat.mem' start='0x700' end='0x800' /><slave name='reg_dp_gain_i.mem' start='0x800' end='0x804' /><slave name='reg_dp_gain_q.mem' start='0x804' end='0x808' /><slave name='reg_dp_gain_u.mem' start='0x808' end='0x80C' /><slave name='reg_dp_gain_v.mem' start='0x80C' end='0x810' /><slave name='rom_unb_system_info.mem' start='0x1000' end='0x2000' /><slave name='reg_tr_xaui.mem' start='0x2000' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='avs_eth_0.mms_ram' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_tab_iquv_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_dp_offload_tx_tab_i_hdr_dat.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_iab_i_hdr_dat.mem' start='0x400' end='0x500' /><slave name='reg_epcs.mem' start='0x500' end='0x520' /><slave name='reg_remu.mem' start='0x520' end='0x540' /><slave name='reg_mdio_2.mem' start='0x540' end='0x560' /><slave name='reg_mdio_1.mem' start='0x560' end='0x580' /><slave name='reg_mdio_0.mem' start='0x580' end='0x5A0' /><slave name='reg_dp_bsn_align_mesh.mem' start='0x5A0' end='0x5C0' /><slave name='pio_wdi.s1' start='0x5C0' end='0x5D0' /><slave name='reg_dp_bsn_align_input.mem' start='0x5D0' end='0x5E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5E0' end='0x5E8' /><slave name='reg_ppsh.mem' start='0x5E8' end='0x5F0' /><slave name='reg_wdi.mem' start='0x5F0' end='0x5F8' /><slave name='reg_dp_xonoff_tab_iquv.mem' start='0x5F8' end='0x600' /><slave name='reg_dp_xonoff_tab_i.mem' start='0x600' end='0x608' /><slave name='reg_dp_xonoff_iab_i.mem' start='0x608' end='0x610' /><slave name='reg_dp_gain_i.mem' start='0x610' end='0x614' /><slave name='reg_dp_gain_q.mem' start='0x614' end='0x618' /><slave name='reg_dp_gain_u.mem' start='0x618' end='0x61C' /><slave name='reg_dp_gain_v.mem' start='0x61C' end='0x620' /><slave name='rom_unb_system_info.mem' start='0x1000' end='0x2000' /><slave name='reg_tr_xaui.mem' start='0x2000' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='avs_eth_0.mms_ram' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="25000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
......@@ -2053,6 +2104,15 @@ q]]></parameter>
<parameter name="g_dat_w" value="16" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
name="reg_dp_xonoff_iab_i">
<parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
</module>
<connection
kind="avalon"
version="11.1"
......@@ -2091,7 +2151,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04e0" />
<parameter name="baseAddress" value="0x05e0" />
</connection>
<connection
kind="interrupt"
......@@ -2106,7 +2166,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04c0" />
<parameter name="baseAddress" value="0x05c0" />
</connection>
<connection
kind="avalon"
......@@ -2258,7 +2318,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0400" />
<parameter name="baseAddress" value="0x0500" />
</connection>
<connection
kind="reset"
......@@ -2281,7 +2341,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0420" />
<parameter name="baseAddress" value="0x0520" />
</connection>
<connection
kind="reset"
......@@ -2304,7 +2364,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_ppsh.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04e8" />
<parameter name="baseAddress" value="0x05e8" />
</connection>
<connection
kind="reset"
......@@ -2373,7 +2433,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_wdi.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04f0" />
<parameter name="baseAddress" value="0x05f0" />
</connection>
<connection
kind="reset"
......@@ -2512,7 +2572,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_2.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0440" />
<parameter name="baseAddress" value="0x0540" />
</connection>
<connection
kind="avalon"
......@@ -2520,7 +2580,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_1.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0460" />
<parameter name="baseAddress" value="0x0560" />
</connection>
<connection
kind="avalon"
......@@ -2528,7 +2588,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mdio_0.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0480" />
<parameter name="baseAddress" value="0x0580" />
</connection>
<connection
kind="avalon"
......@@ -2682,7 +2742,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_bsn_align_input.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04d0" />
<parameter name="baseAddress" value="0x05d0" />
</connection>
<connection
kind="clock"
......@@ -2705,7 +2765,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_bsn_align_mesh.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04a0" />
<parameter name="baseAddress" value="0x05a0" />
</connection>
<connection
kind="clock"
......@@ -2728,7 +2788,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_xonoff_tab_iquv.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04f8" />
<parameter name="baseAddress" value="0x05f8" />
</connection>
<connection
kind="clock"
......@@ -2787,7 +2847,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_xonoff_tab_i.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0500" />
<parameter name="baseAddress" value="0x0600" />
</connection>
<connection
kind="clock"
......@@ -2800,7 +2860,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_iab_i_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0700" />
<parameter name="baseAddress" value="0x0400" />
</connection>
<connection
kind="clock"
......@@ -2813,7 +2873,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_gain_i.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0800" />
<parameter name="baseAddress" value="0x0610" />
</connection>
<connection
kind="reset"
......@@ -2841,7 +2901,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_gain_q.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0804" />
<parameter name="baseAddress" value="0x0614" />
</connection>
<connection
kind="reset"
......@@ -2869,7 +2929,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_gain_u.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0808" />
<parameter name="baseAddress" value="0x0618" />
</connection>
<connection
kind="avalon"
......@@ -2877,6 +2937,24 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_gain_v.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x080c" />
<parameter name="baseAddress" value="0x061c" />
</connection>
<connection
kind="clock"
version="11.1"
start="clk_input.clk"
end="reg_dp_xonoff_iab_i.system" />
<connection
kind="reset"
version="11.1"
start="clk_input.clk_reset"
end="reg_dp_xonoff_iab_i.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_dp_xonoff_iab_i.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0608" />
</connection>
</system>
applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
+ 8
− 0
View file @ 3d197edc
......@@ -169,6 +169,9 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
SIGNAL reg_dp_xonoff_tab_i_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_xonoff_tab_i_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_dp_xonoff_iab_i_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_xonoff_iab_i_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_dp_offload_tx_tab_i_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_offload_tx_tab_i_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
......@@ -365,6 +368,8 @@ BEGIN
iab_src_in => arts_unb1_sc4_output_iab_src_in_arr(0),
reg_dp_offload_tx_iab_i_hdr_dat_mosi => reg_dp_offload_tx_iab_i_hdr_dat_mosi,
reg_dp_offload_tx_iab_i_hdr_dat_miso => reg_dp_offload_tx_iab_i_hdr_dat_miso,
reg_dp_xonoff_iab_i_mosi => reg_dp_xonoff_iab_i_mosi,
reg_dp_xonoff_iab_i_miso => reg_dp_xonoff_iab_i_miso,
ID => ID
);
......@@ -533,6 +538,9 @@ BEGIN
reg_dp_offload_tx_iab_i_hdr_dat_mosi => reg_dp_offload_tx_iab_i_hdr_dat_mosi,
reg_dp_offload_tx_iab_i_hdr_dat_miso => reg_dp_offload_tx_iab_i_hdr_dat_miso,
reg_dp_xonoff_iab_i_mosi => reg_dp_xonoff_iab_i_mosi,
reg_dp_xonoff_iab_i_miso => reg_dp_xonoff_iab_i_miso,
reg_dp_gain_i_mosi => reg_dp_gain_i_mosi,
reg_dp_gain_i_miso => reg_dp_gain_i_miso,
reg_dp_gain_q_mosi => reg_dp_gain_q_mosi,
......
applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_mm_master.vhd
+ 19
− 0
View file @ 3d197edc
......@@ -97,6 +97,8 @@ ENTITY arts_unb1_sc4_mm_master IS
reg_dp_offload_tx_tab_iquv_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_xonoff_tab_i_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_xonoff_tab_i_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_xonoff_iab_i_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_xonoff_iab_i_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_tab_i_hdr_dat_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_offload_tx_tab_i_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_iab_i_hdr_dat_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
......@@ -349,6 +351,14 @@ ARCHITECTURE str OF arts_unb1_sc4_mm_master IS
reg_dp_xonoff_tab_i_write_export : OUT STD_LOGIC;
reg_dp_xonoff_tab_i_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_dp_xonoff_iab_i_address_export : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0);
-- reg_dp_xonoff_iab_i_clk_export : OUT STD_LOGIC;
reg_dp_xonoff_iab_i_read_export : OUT STD_LOGIC;
reg_dp_xonoff_iab_i_readdata_export : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-- reg_dp_xonoff_iab_i_reset_export : OUT STD_LOGIC;
reg_dp_xonoff_iab_i_write_export : OUT STD_LOGIC;
reg_dp_xonoff_iab_i_writedata_export : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
reg_dp_offload_tx_tab_iquv_hdr_dat_address_export : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0);
-- reg_dp_offload_tx_tab_iquv_hdr_dat_clk_export : OUT STD_LOGIC;
reg_dp_offload_tx_tab_iquv_hdr_dat_read_export : OUT STD_LOGIC;
......@@ -430,6 +440,7 @@ BEGIN
reg_dp_xonoff_tab_iquv_mosi <= c_mem_mosi_rst;
reg_dp_offload_tx_tab_iquv_hdr_dat_mosi <= c_mem_mosi_rst;
reg_dp_xonoff_tab_i_mosi <= c_mem_mosi_rst;
reg_dp_xonoff_iab_i_mosi <= c_mem_mosi_rst;
reg_dp_offload_tx_tab_i_hdr_dat_mosi <= c_mem_mosi_rst;
reg_dp_offload_tx_iab_i_hdr_dat_mosi <= c_mem_mosi_rst;
reg_dp_bsn_align_input_mosi <= c_mem_mosi_rst;
......@@ -679,6 +690,14 @@ BEGIN
reg_dp_xonoff_tab_i_write_export => reg_dp_xonoff_tab_i_mosi.wr,
reg_dp_xonoff_tab_i_writedata_export => reg_dp_xonoff_tab_i_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_xonoff_iab_i_address_export => reg_dp_xonoff_iab_i_mosi.address(1-1 DOWNTO 0),
-- reg_dp_xonoff_iab_i_clk_export => OPEN,
reg_dp_xonoff_iab_i_read_export => reg_dp_xonoff_iab_i_mosi.rd,
reg_dp_xonoff_iab_i_readdata_export => reg_dp_xonoff_iab_i_miso.rddata(c_word_w-1 DOWNTO 0),
-- reg_dp_xonoff_iab_i_reset_export => OPEN,
reg_dp_xonoff_iab_i_write_export => reg_dp_xonoff_iab_i_mosi.wr,
reg_dp_xonoff_iab_i_writedata_export => reg_dp_xonoff_iab_i_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_tab_i_hdr_dat_address_export => reg_dp_offload_tx_tab_i_hdr_dat_mosi.address(6-1 DOWNTO 0),
-- reg_dp_offload_tx_tab_i_hdr_dat_clk_export => OPEN,
reg_dp_offload_tx_tab_i_hdr_dat_read_export => reg_dp_offload_tx_tab_i_hdr_dat_mosi.rd,
......
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