-Removed unnecessary bits;

-Added eth_statistics instance.

applications/arts/designs/arts_unb1_sc1_bg_1GbE/tb/vhdl/tb_arts_unb1_sc1_bg_1GbE.vhd

 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2012
+-- Copyright (C) 2016
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -20,29 +20,11 @@
 --
 -------------------------------------------------------------------------------
 
--- Purpose: Test bench for arts_unb1_sc1_bg_1GbE.
+-- Purpose:
 -- Description:
---   The DUT can be targeted at unb 0, bn3 with the same Python scripts 
---   that are used on hardware. 
--- Usage:
---   On command line do:
---     > run_modelsim & (to start Modeslim)
---
---   In Modelsim do:
---     > lp arts_unb1_sc1_bg_1GbE
---     > mk clean all (only first time to clean all libraries)
---     > mk all (to compile all libraries that are needed for arts_unb1_sc1_bg_1GbE)
---     . load tb_arts_unb1_sc1_bg_1GbE simulation by double clicking the tb_arts_unb1_sc1_bg_1GbE icon
---     > as 10 (to view signals in Wave Window)
---     > run 100 us (or run -all)
---
---   On command line do:
---     > python $UPE/peripherals/util_system_info.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_unb_sens.py --unb 0 --bn 3 -n 0 -v 5 --sim
---     > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
 --
 
-LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, eth_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
@@ -50,11 +32,6 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
 
 ENTITY tb_arts_unb1_sc1_bg_1GbE IS
-    GENERIC (
-      g_design_name : STRING  := "arts_unb1_sc1_bg_1GbE";
-      g_sim_unb_nr  : NATURAL := 0; -- UniBoard 0
-      g_sim_node_nr : NATURAL := 7  -- Back node 3
-    );
 END tb_arts_unb1_sc1_bg_1GbE;
 
 ARCHITECTURE tb OF tb_arts_unb1_sc1_bg_1GbE IS
@@ -68,7 +45,6 @@ ARCHITECTURE tb OF tb_arts_unb1_sc1_bg_1GbE IS
   CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
   CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
 
-  CONSTANT c_cable_delay     : TIME := 12 ns;
   CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
   CONSTANT c_clk_period      : TIME := 5 ns; 
   CONSTANT c_pps_period      : NATURAL := 1000; 
@@ -83,27 +59,15 @@ ARCHITECTURE tb OF tb_arts_unb1_sc1_bg_1GbE IS
   SIGNAL INTB                : STD_LOGIC;
 
   SIGNAL eth_clk             : STD_LOGIC := '0';
-  SIGNAL eth_txp             : STD_LOGIC;
-  SIGNAL eth_rxp             : STD_LOGIC;
 
   SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
   SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
   SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
 
-  SIGNAL sens_scl            : STD_LOGIC;
-  SIGNAL sens_sda            : STD_LOGIC;
-
-  -- Model I2C sensor slaves as on the UniBoard
-  CONSTANT c_fpga_temp_address   : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000";  -- MAX1618 address LOW LOW
-  CONSTANT c_fpga_temp           : INTEGER := 60;
-  CONSTANT c_eth_temp_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001";  -- MAX1618 address MID LOW
-  CONSTANT c_eth_temp            : INTEGER := 40;
-  CONSTANT c_hot_swap_address    : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100";  -- LTC4260 address L L L
-  CONSTANT c_hot_swap_R_sense    : REAL := 0.01;                               -- = 10 mOhm on UniBoard
-  
-  CONSTANT c_uniboard_current    : REAL := 5.0;   -- = assume 5.0 A on UniBoard
-  CONSTANT c_uniboard_supply     : REAL := 48.0;  -- = assume 48.0 V on UniBoard
-  CONSTANT c_uniboard_adin       : REAL := -1.0;  -- = NC on UniBoard
+  -- Ethernet stats
+  SIGNAL eth_statistics_serial_in : STD_LOGIC;
+  SIGNAL eth_statistics_pkt_cnt   : NATURAL;
+  SIGNAL eth_statistics_pkt_len   : NATURAL;
 
 BEGIN
 
@@ -113,22 +77,11 @@ BEGIN
   clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
   eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
   
-  INTA <= 'H';  -- pull up
-  INTB <= 'H';  -- pull up
-
-  sens_scl <= 'H';  -- pull up
-  sens_sda <= 'H';  -- pull up
-
   ------------------------------------------------------------------------------
   -- External PPS
   ------------------------------------------------------------------------------  
   proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
  
-  ------------------------------------------------------------------------------
-  -- 1GbE Loopback model
-  ------------------------------------------------------------------------------  
-  eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
-  
   ------------------------------------------------------------------------------
   -- DUT
   ------------------------------------------------------------------------------
@@ -137,63 +90,28 @@ BEGIN
       g_sim         => c_sim
     )
     PORT MAP (
-      -- GENERAL
       CLK         => clk,
       PPS         => pps,
-      WDI         => WDI,
-      INTA        => INTA,
-      INTB        => INTB,
-
-      sens_sc     => sens_scl,
-      sens_sd     => sens_sda,
 
-      -- Others
       VERSION     => VERSION,
       ID          => ID,
       TESTIO      => TESTIO,
 
-      -- 1GbE Control Interface
       ETH_clk     => eth_clk,
-      ETH_SGIN    => eth_rxp,
-      ETH_SGOUT   => eth_txp
+      ETH_SGIN    => '0',
+      ETH_SGOUT   => eth_statistics_serial_in
     );
 
   ------------------------------------------------------------------------------
-  -- UniBoard sensors
+  -- Verify proper DUT output using Ethernet packet statistics
   ------------------------------------------------------------------------------
-  -- I2C slaves that are available for each FPGA
-  u_fpga_temp : ENTITY i2c_lib.dev_max1618
-  GENERIC MAP (
-    g_address => c_fpga_temp_address
-  )
+  u_eth_statistics : ENTITY eth_lib.eth_statistics
   PORT MAP (  
-    scl  => sens_scl,
-    sda  => sens_sda,
-    temp => c_fpga_temp
-  );
+    eth_clk       => eth_clk,
+    eth_serial_in => eth_statistics_serial_in,
 
-  -- I2C slaves that are available only via FPGA back node 3
-  u_eth_temp : ENTITY i2c_lib.dev_max1618
-  GENERIC MAP (
-    g_address => c_eth_temp_address
-  )
-  PORT MAP (
-    scl  => sens_scl,
-    sda  => sens_sda,
-    temp => c_eth_temp
-  );
-  
-  u_power : ENTITY i2c_lib.dev_ltc4260
-  GENERIC MAP (
-    g_address => c_hot_swap_address,
-    g_R_sense => c_hot_swap_R_sense
-  )
-  PORT MAP (
-    scl               => sens_scl,
-    sda               => sens_sda,
-    ana_current_sense => c_uniboard_current,
-    ana_volt_source   => c_uniboard_supply,
-    ana_volt_adin     => c_uniboard_adin
+    pkt_cnt       => eth_statistics_pkt_cnt,
+    pkt_len       => eth_statistics_pkt_len
   );
 
 END tb;