Added bsn_monitor

Changed data_width 
Upated firmware-version

applications/apertif/designs/apertif_unb1_cor_mesh_ref/src/vhdl/apertif_unb1_cor_mesh_ref.vhd

@@ -87,12 +87,12 @@ END apertif_unb1_cor_mesh_ref;
 ARCHITECTURE str OF apertif_unb1_cor_mesh_ref IS
   
   CONSTANT c_use_phy                 : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);         
-  CONSTANT c_fw_version              : t_unb1_board_fw_version := (0, 1);  -- firmware version x.y 
+  CONSTANT c_fw_version              : t_unb1_board_fw_version := (0, 5);  -- firmware version x.y 
                                      
   CONSTANT c_node_type               : t_e_unb1_board_node := e_any;   -- or e_fn, or e_bn
   CONSTANT c_nof_bus                 : NATURAL := 4;      -- one bus to each of the 4 nodes on the other side of the mesh
   CONSTANT c_usr_use_complex         : BOOLEAN := TRUE;   -- when TRUE transport sosi im & re fields via DP data, else transport sosi data via DP data
-  CONSTANT c_usr_data_w              : NATURAL := 8;      -- <= 32, to avoid need for DP packet data packing and to fit on the tr_nonbonded PHY data width of 32 bit
+  CONSTANT c_usr_data_w              : NATURAL := 16;    -- 16 = 2 x c_complex_w = 2 x 8 
   CONSTANT c_usr_frame_len           : NATURAL := 128; --20;
   CONSTANT c_usr_nof_streams         : NATURAL := 3;      -- number of user streams per bus
   CONSTANT c_phy_nof_serial          : NATURAL := 3;      -- up to 4 serial lanes per bus
@@ -104,7 +104,7 @@ ARCHITECTURE str OF apertif_unb1_cor_mesh_ref IS
   CONSTANT c_tx_input_fifo_size      : NATURAL := c_bram_m9k_fifo_depth;   -- g_tx_input_use_fifo=TRUE, choose to use full BRAM size = 256 for FIFO depth at input to uth_terminal_tx
   CONSTANT c_tx_input_fifo_fill      : NATURAL := 0;
   CONSTANT c_use_rx                  : BOOLEAN := TRUE;
-  CONSTANT c_rx_output_use_fifo      : BOOLEAN := FALSE;   -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+  CONSTANT c_rx_output_use_fifo      : BOOLEAN := TRUE;   -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
   CONSTANT c_rx_output_fifo_size     : NATURAL := c_bram_m9k_fifo_depth;   -- g_rx_output_use_fifo, choose to use full BRAM size = 256 for FIFO depth at output of uth_terminal_rx
   CONSTANT c_rx_output_fifo_fill     : NATURAL := 0;
   CONSTANT c_rx_timeout_w            : NATURAL := 0;      -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
@@ -121,8 +121,6 @@ ARCHITECTURE str OF apertif_unb1_cor_mesh_ref IS
   CONSTANT c_mesh_mon_nof_words      : NATURAL := c_unb1_board_peripherals_mm_reg_default.ram_diag_db_buf_size;  -- = 1024
   CONSTANT c_mesh_mon_use_sync       : BOOLEAN := TRUE;  -- when TRUE use dp_pps to trigger the data buffer capture, else new data capture after read access of last data word
                                      
-  CONSTANT c_reg_diag_db_adr_w       : NATURAL := 5;
-
   -- System
   SIGNAL cs_sim                      : STD_LOGIC;
   SIGNAL xo_clk                      : STD_LOGIC;
@@ -200,9 +198,13 @@ ARCHITECTURE str OF apertif_unb1_cor_mesh_ref IS
   SIGNAL ram_diag_data_buf_im_mosi   : t_mem_mosi := c_mem_mosi_rst;
   SIGNAL ram_diag_data_buf_im_miso   : t_mem_miso;
   SIGNAL reg_diag_data_buf_im_mosi   : t_mem_mosi := c_mem_mosi_rst;
-  SIGNAL reg_diag_data_buf_im_miso   : t_mem_miso;  
-
-BEGIN
+  SIGNAL reg_diag_data_buf_im_miso   : t_mem_miso;    
+  
+  -- MM bsn_monitor
+  SIGNAL reg_bsn_monitor_mosi        : t_mem_mosi := c_mem_mosi_rst;  
+  SIGNAL reg_bsn_monitor_miso        : t_mem_miso;                    
+  
+BEGIN                                                                 
 
   -----------------------------------------------------------------------------
   -- General control function
@@ -351,7 +353,9 @@ BEGIN
      reg_diagnostics_mosi       =>  reg_diagnostics_mosi,
      reg_diagnostics_miso       =>  reg_diagnostics_miso,
      reg_tr_nonbonded_mosi      =>  reg_tr_nonbonded_mosi,
-     reg_tr_nonbonded_miso      =>  reg_tr_nonbonded_miso
+     reg_tr_nonbonded_miso      =>  reg_tr_nonbonded_miso,
+     reg_bsn_monitor_mosi       =>  reg_bsn_monitor_mosi,
+     reg_bsn_monitor_miso       =>  reg_bsn_monitor_miso      
    );
  
   -----------------------------------------------------------------------------
@@ -427,7 +431,8 @@ BEGIN
     reg_tr_nonbonded_miso       => reg_tr_nonbonded_miso,      
     reg_diagnostics_mosi        => reg_diagnostics_mosi,       
     reg_diagnostics_miso        => reg_diagnostics_miso, 
-
+    reg_bsn_monitor_mosi        => reg_bsn_monitor_mosi,
+    reg_bsn_monitor_miso        => reg_bsn_monitor_miso,
     -- Mesh serial interface (tr_nonbonded)
     tx_serial_2arr              => tx_serial_2arr, 
     rx_serial_2arr              => rx_serial_2arr